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US5562971A Expired / Lapsed US ⏱️ 0.0 years remaining

Multilayer printed wiring board

Assignee: Resonac Corp
•
Filing: 1995-04-07
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Granted: 1996-10-08
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Expires: 2015-04-07
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Abstract

Abstract A multilayer printed wiring board comprising a plurality of interlaminar insulating layers, a plurality of insulating circuit boards having circuits formed on the insulating substrates, and via holes for making electrical connection between two or more layers of circuits, wherein the difference between the glass transition point of an interlaminar insulating layer and that of the adjoining insulating substrate is not greater than 60° C., is proof against exfoliation due to heat history of the board and has high reliability of insulation and through-hole connection.

Inventors

  • 👤 Yoshiyuki Tsuru
  • 👤 Shigeharu Arike
  • 👤 Takashi Sugiyama
  • 👤 Shinjirou Miyashita
  • 👤 Takayuki Suzuki

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-03 14:44
CPC Classifications
H; H05; H05K; H05K3/00; H05K3/46; H05K3/4688; H05K1/00; H05K1/02; H05K3/4611; H05K3/4623; H05K3/4626; H05K3/4697; H10; H10W; H10W70/00; H10W70/01; H10W70/05; H10W70/60; H10W70/611; H10W70/67; H10W70/68; H10W70/685; H10W70/69; H10W70/695; H05K2201/00; H05K2201/01; H05K2201/0137; H05K2201/0154; H05K3/4644; H05K3/4673; H05K3/4676; H10W70/682; H10W72/00; H10W72/071; H10W72/075; H10W72/07551; H10W72/07554; H10W72/50; H10W72/531; H10W72/5363; H10W72/541; H10W72/547; H10W90/00; H10W90/701; H10W90/751; H10W90/754; Y; Y10; Y10T; Y10T428/00; Y10T428/24; Y10T428/24802; Y10T428/24917

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 125 words
A multilayer printed wiring board comprising a plurality of interlaminar insulating layers made from a thermosetting resin having a B-stage, a plurality of insulating substrates made from a thermosetting resin containing a fiber reinforcement, circuits formed on the surface of said insulating substrates, and via holes for making electrical connection between two or more layers of circuits, said via holes running through two layers of insulating substrate and an interlaminar insulating layer disposed there-between; said interlaminar insulating layers being each an insulating layer containing no reinforcement; the B-stage resin flow of said interlaminar insulating layers being less than 1%; and the difference between the glass transition point of each interlaminar insulating layer and that of the adjoining insulating substrate being not greater than 60° C.
Claim 2
Dependent Claim 125 words
A multilayer printed wiring board comprising a plurality of interlaminar insulating layers made from a thermosetting resin having a B-stage, a plurality of insulating substrates made from a thermosetting resin containing a fiber reinforcement, circuits formed on the surface of said insulating substrates, and via holes for making electrical connection between two or more layers of circuits, said via holes running through two layers of insulating substrate and an interlaminar insulating layer disposed there-between; said interlaminar insulating layers being each an insulating layer containing no reinforcement; the B-stage resin flow of said interlaminar insulating layers being less than 1%; and the difference between the glass transition point of each interlaminar insulating layer and that of the adjoining insulating substrate being not greater than 60° C.
Claim 3
Dependent Claim 47 words
A multilayer printed wiring board according to claim 1, wherein the B-stage viscoelasticity of the interlaminar insulating layers is in the range of 2,000-5,000 MPa at 30° C. and in the range below 10 MPa at a molding temperature for the thermosetting resin of the insulating layers.
Claim 4
Dependent Claim 34 words
A multilayer printed wiring board according to claim 1, wherein cavities for housing semiconductor chips to be mounted later are formed in one or more of the interlaminar insulating layers or the insulating substrates.
Claim 5
Dependent Claim 76 words
A multilayer printed wiring board according to claim 1, wherein the cavities are enlarged in size successively from the one in the interlaminar insulating layer or insulating substrate closest to the location where the semiconductor chips are to be set, and terminals for making electrical connection with the semiconductor chips to be mounted later are provided in the circuits formed on the surfaces of the interlaminar insulating layers or insulating substrates exposed by the respective cavities.
Claim 6
Dependent Claim 30 words
A multilayer printed wiring board according to claim 4, wherein said cavities are through-holes, and a heat sink is provided closing one of the openings of each of said through-holes.
Claim 7
Dependent Claim 47 words
A multilayer printed wiring board according to claim 3, wherein terminals for making electrical connection with other wiring boards are provided on one side of the board and openings for mounting semiconductor chips are formed in the same side or in the opposite side of the board.
Claim 8
Dependent Claim 22 words
A multilayer printed wiring board according to claim 6, wherein the terminals for making electrical connection with other wiring boards are pins.
Claim 9
Dependent Claim 30 words
A multilayer printed wiring board according to claim 6, wherein the terminals for making electrical connection with other wiring boards are lands designed for making electrical connection by solder balls.
Claim 10
Dependent Claim 236 words
A multilayer printed wiring board according to claim 1, wherein at least one of the interlaminar insulating layers or insulating substrates having via holes running there-through is composed of a thermosetting resin comprising 40-70% by weight of a polyimide represented by the following formula (1), 14-45% by weight of a bismaleimide-diamine reaction product and 15-45% by weight of an epoxy resin: ##STR4## wherein Ar is a group represented by the following formula (2) or (3), the group of the formula (2) being contained in an amount of 10-98% by mole and the group of the formula (3) being contained in an amount of 90-5% by mole: ##STR5## wherein Z represents --C(═O)--, --SO 2 --, --O--, --S--, --(CH 2 ) m --, --NH--C(═O)--, --C(CH 3 ) 2 --, --C(CF 3 ) 2 --, --C(═O)--O-- or a bond; n and m are each an integer of 1 or greater; each Z may be the same or different from the other, and each hydrogen in each benzene ring may be substituted with an appropriate substituent; ##STR6## wherein R 1 , R 2 , R 3 and R 4 represent independently hydrogen, C 1-4 alkyl group or alkoxy group with at least two of R 1 , R 2 , R 3 and R 4 being an alkyl group or alkoxy group; and x represents --CH 2 --, --C(CH 3 ) 2 --, --O--, --SO 2 --, --C(═O)-- or --NH--C(═O)--.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1999-10-08 2000-04-08 2000-10-08 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2003-10-08 2004-04-08 2004-10-08 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2007-10-08 2008-04-08 2008-10-08 $7700.00 Window Closed / Lapsed

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