Pseudo static mask option register and method therefor

Claim 2

A data processing system, comprising: an interface means for providing a mask option program value; input means for providing a reset signal; a system clock circuit for generating a system clock signal; a first peripheral device for executing a first predetermined data processing function in response to a first enable signal; and a main memory for storing a plurality of main memory values; a mask option register having a first input coupled to the interface means for receiving the mask option program value, a second input coupled to the system clock circuit for receiving the system clock signal, and an output for providing the first enable signal, the mask option register, comprising: logic means for generating a refresh signal in response to the system clock signal and the reset signal; a plurality of programmable memory bits for collectively storing the mask option program value, each of the plurality of memory bits providing a bit of the mask option program value; a plurality of sense amplifier circuits coupled to the plurality of memory bits for sensing a logic value of the mask option program value collectively provided by the plurality of memory bits in response to the refresh signal; and a plurality of static latches for collectively storing the mask option program value, the plurality of static latches being periodically refreshed in response to the refresh signal, a first one of the plurality of static latches providing the first enable signal.

Claim 3

The data processing system of claim 1 wherein the input means comprises a first integrated circuit pin for providing a reset signal.

Claim 4

The data processing system of claim 2 further comprising: a central processing unit for providing a no clock signal to indicate the system clock signal will not be generated by the system clock circuit, wherein the logic means logically combines each of the system clock signal, the reset signal, and the no clock signal to provide the refresh signal.

Claim 5

The data processing system of claim 1 further comprising: a second peripheral device for executing a second predetermined data processing function in response to a second enable signal.

Claim 6

The data processing system of claim 4 wherein a second one of the plurality of static latches provides the second enable signal.

Claim 7

The data processing system of claim 1 wherein the plurality of memory bits are implemented as a non-volatile memory.

Claim 8

The data processing system of claim 1 wherein the plurality of memory bits are an electrically programmable read only memory (EPROM).

Claim 9

The data processing system of claim 1 wherein the main memory and the plurality of memory bits comprising the mask option register are physically separate.

Claim 10

The data processing system of claim 1 wherein the main memory and the plurality of memory bits are a same type of non-volatile memory.

Claim 11

The data processing system of claim 1 wherein the main memory is implemented as a first type of non-volatile memory and the plurality of memory bits are implemented as a second type of non-volatile memory.

Claim 14

The method of claim 11 wherein a first one of the plurality of static latches provides a first enable signal, the first enable signal being used to enable a peripheral device to perform a first data processing function.

Claim 15

The method of claim 12 further comprising the steps of: providing a reset signal; providing a clock absent signal; and logically combining each of the system clock signal, the reset signal, and the clock absent signal to provide the refresh signal.

Claim 16

The method of claim 11 wherein the plurality of memory bits are implemented as a non-volatile memory.

Claim 17

The method of claim 11 wherein the plurality of memory bits are an electrically programmable read only memory (EPROM).

Claim 18

A data processing system, comprising: a central processing unit for processing a plurality of data processing functions, the central processing unit providing a mask option program value; a system clock circuit for generating a system clock signal; a first peripheral device for executing a first predetermined data processing function in response to a first enable signal; and a main memory for storing a plurality of main memory values; a mask option register having a first input coupled to the central processing unit for receiving the mask option program value, a second input coupled to the system clock circuit for receiving the system clock signal, and an output for providing the enable signal, the mask option register, comprising: logic means for generating a refresh signal in response to the system clock signal; a first transistor having a fist terminal coupled to a first voltage value, a second terminal coupled to a reference voltage value, and a third terminal; a current source circuit having an output coupled to the third terminal of the first transistor, a first input coupled to the logical means for receiving the refresh signal, and a second input coupled to the first voltage value; a current sensor circuit having an input coupled to the third terminal of the first transistor, the current sensor circuit having an output for indicating when the first transistor conducts current; a latching means having an input coupled to the output of the current sensor circuit, the latching means maintaining a logic value of the output of the current sensor circuit, the latching means having an output; and a buffer having an input coupled to the output of the current sensor circuit for providing the first enable signal.

Claim 19

A data processing system, comprising: a central processing unit for processing a plurality of data processing functions, the central processing unit providing a mask option program value; a system clock circuit for generating a system clock signal; a first peripheral device for executing a first predetermined data processing function in response to a first enable signal; and a main memory for storing a plurality of main memory values; a mask option register having a first input coupled to the central processing unit for receiving the mask option program value, a second input coupled to the system clock circuit for receiving the system clock signal, and an output for providing the enable signal, the mask option register, comprising: logic means for generating a refresh signal in response to the system clock signal; a first transistor having a fist terminal coupled to a first voltage value, a second terminal coupled to a reference voltage value, and a third terminal; a current source circuit having an output coupled to the third terminal of the first transistor, a first input coupled to the logical means for receiving the refresh signal, and a second input coupled to the first voltage value; a current sensor circuit having an input coupled to the third terminal of the first transistor, the current sensor circuit having an output for indicating when the first transistor conducts current; a latching means having an input coupled to the output of the current sensor circuit, the latching means maintaining a logic value of the output of the current sensor circuit, the latching means having an output; and a buffer having an input coupled to the output of the current sensor circuit for providing the first enable signal.

Claim 20

The data processing system of claim 16 further comprising: a first integrated circuit pin for providing a reset signal.

Claim 21

The data processing system of claim 17 wherein the logic means logically combines each of the system clock signal, the reset signal, and a clock absent signal to provide the refresh signal.

Claim 22

The data processing system of claim 16 further comprising: a second peripheral device for executing a second predetermined data processing function in response to a second enable signal.

Claim 23

The data processing system of claim 16 wherein the plurality of memory bits are implemented as a non-volatile memory.

Claim 24

The data processing system of claim 16 wherein the main memory and the plurality of memory bits comprising the mask option register are physically separate.

Claim 25

A mask option register, comprising: input means for receiving a plurality of control signals; logic means for logically combining the plurality of control signals to provide a refresh clock signal, the logic means being coupled to the input means for receiving the plurality of control signals; a plurality of programmable memory bits for communicating a mask option program value; a plurality of sense amplifiers coupled to the logic means for receiving the refresh clock signal and coupled to the plurality of programmable memory bits for communicating the mask option program value, the plurality of sense amplifiers sensing the mask option program value; and a plurality of static latches for selectively storing the mask option program value, each of the plurality of static latches being periodically refreshed in response to the refresh clock signal.

Claim 26

A mask option register, comprising: input means for receiving a plurality of control signals; logic means for logically combining the plurality of control signals to provide a refresh clock signal, the logic means being coupled to the input means for receiving the plurality of control signals; a plurality of programmable memory bits for communicating a mask option program value; a plurality of sense amplifiers coupled to the logic means for receiving the refresh clock signal and coupled to the plurality of programmable memory bits for communicating the mask option program value, the plurality of sense amplifiers sensing the mask option program value; and a plurality of static latches for selectively storing the mask option program value, each of the plurality of static latches being periodically refreshed in response to the refresh clock signal.

Claim 27

The mask option register of claim 22 wherein the plurality of programmable memory bits are implemented as an electrically programmable read only memory.

Claim 28

The mask option register of claim 22 wherein the plurality of control signals includes a reset signal, a system clock signal, and a clock absence signal.

Claim 29

The mask option register of claim 24 wherein the clock absence signal is provided to indicate the system clock signal will not be generated.