US5307464A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Microprocessor and method for setting up its peripheral functions
Assignee: Hitachi Ltd
•
Filing: 1990-12-03
•
Granted: 1994-04-26
•
Expires: 2010-12-03
Abstract
Abstract A single chip microprocessor 1 includes a CPU 2 and a sub-processor 5 for software implementation of peripheral functions of the microprocessor 1. Sub-processor 5 includes electrically writable internal storage devices microprogram memory unit 13 and sequence control memory unit 62 for storing the software. Peripheral functions are defined and/or modified by writing software into the memory units 13 and 62. Accordingly, the time it takes to define and/or modify the peripheral functions is the time it takes to program the memory units 13 and 62. The sub-processor 5 also includes an execution unit 16 for executing a plurality of tasks and an address control circuit 14 for providing addresses to the microprogram memory unit 13. Additionally, the microprogram memory unit 13 provides microinstructions to the execution unit 16. The sequence control memory unit 62 is part of the address control circuit 14 which also includes a plurality of address registers MAR0 to MAR11. The sequence control memory unit 62 is used for storing information regarding the order of selection of the multiple address registers MAR0 to MAR11. One of the address registers MAR0 to MAR11 is selected each time the sequence control memory unit 62 is read. A microaddress stored in the selected address register is then supplied to the microprogram memory unit 13.
Inventors
- 👤 Yasushi Akao
- 👤 Shiro Baba
- 👤 Yoshiyuki Miwa
- 👤 Terumi Sawase
- 👤 Yuji Sato
- 👤 Shigeki Masumura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 12:14
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/10; G06F13/12; G06F13/124; G06F15/00; G06F15/76; G06F15/78; G06F15/7807; G06F15/7814
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
102 words
A method of setting peripheral functions of a microprocessor using a computer system, the method comprising the steps of: displaying a menu of functions for information provided in advance for defining peripheral functions implementable by a peripheral function implementing means in the microprocessor on a display screen of the computer system; retrieving the information for defining a peripheral function corresponding to a function selected from the menu of functions from storage media of the computer system; and transmitting the retrieved information from the computer system to a writing apparatus for programming electrically writable non-volatile memory elements of said peripheral function implementing means.
Claim 2
Independent Claim
102 words
A method of setting peripheral functions of a microprocessor using a computer system, the method comprising the steps of: displaying a menu of functions for information provided in advance for defining peripheral functions implementable by a peripheral function implementing means in the microprocessor on a display screen of the computer system; retrieving the information for defining a peripheral function corresponding to a function selected from the menu of functions from storage media of the computer system; and transmitting the retrieved information from the computer system to a writing apparatus for programming electrically writable non-volatile memory elements of said peripheral function implementing means.
Claim 3
Dependent Claim
32 words
The method according to claim 1, further comprising the step of writing the transmitted information into the electrically writable non-volatile memory elements of said peripheral function implementing means by the writing apparatus.
Claim 4
Dependent Claim
83 words
The method according to claim 2, further comprising the steps of: erasing the information written into the electrically writable non-volatile memory elements of said peripheral function implementing means if it is necessary to change the peripheral function which has been once set in said peripheral function implementing means; and, writing modified information, which is obtained by repeating the displaying step, the retrieving step, the transmitting step and the writing step, into the electrically writable non-volatile memory elements of said peripheral function implementing means.
Claim 5
Dependent Claim
27 words
The method according to claim 1, further comprising the step of selecting a desired function from the menu of functions by a keyboard of the computer system.
Claim 6
Dependent Claim
27 words
The method according to claim 1, further comprising a step of selecting a desired function from the menu of functions by a mouse of the computer system.
Claim 7
Dependent Claim
14 words
The method according to claim 1, wherein the storage media includes a floppy disk.
Claim 8
Dependent Claim
101 words
A microcomputer comprising: a memory unit for storing, in address locations of the memory unit, a task execution order in which a plurality of tasks are to be executed; a register; a plurality of counters; and an address generating means in operable connection with said register and said plurality of counters for generating addresses by combining contents of said register and said plurality of counters, wherein the plurality of tasks are executed one after another in accordance with the task execution order read from the address locations of said memory unit according to the addresses generated by said address generating means.
Claim 9
Dependent Claim
101 words
A microcomputer comprising: a memory unit for storing, in address locations of the memory unit, a task execution order in which a plurality of tasks are to be executed; a register; a plurality of counters; and an address generating means in operable connection with said register and said plurality of counters for generating addresses by combining contents of said register and said plurality of counters, wherein the plurality of tasks are executed one after another in accordance with the task execution order read from the address locations of said memory unit according to the addresses generated by said address generating means.
Claim 10
Dependent Claim
48 words
A microcomputer according to claim 7, wherein said memory unit is used for storing identification numbers for identifying the plurality of tasks and a control coded for controlling said register and said plurality of counters and said memory unit generates addresses in accordance with said stored control code.
Claim 11
Dependent Claim
47 words
A microcomputer according to claim 8, wherein said control code comprises first control information for specifying initialization and counting-up of said plurality of counters and second control information for specifying how said register is to be combined with said plurality of counters in generating the memory addresses.
Claim 12
Dependent Claim
57 words
A microcomputer according to claim 7, wherein the microcomputer is formed on a single semiconductor chip and further comprises a plurality of means for setting a value in said register, with one of said plurality of means allowing a value to be set in said register from a source external of the semiconductor chip of said microcomputer.
Claim 13
Dependent Claim
62 words
A microcomputer according to claim 7, wherein a means for executing a plurality of tasks comprises a memory unit for storing execution programs of the plurality of tasks and a plurality of address registers for holding read addresses of said memory unit and generates addresses for reading said memory unit based on the read addresses held in said plurality of address registers.
Claim 14
Dependent Claim
33 words
A microcomputer according to claim 11, wherein predetermined values can be set in said plurality of address registers without regard to a current sequence of tasks execution according to the selected address registers.
Claim 15
Dependent Claim
25 words
A microcomputer according to claim 7, wherein the execution memory unit is read based on task identification numbers corresponding to said plurality of address registers.
References Cited (Backward Citations)
US3753236A
Cited
US4153933A
Cited
US4079452A
Cited
EP0111161A2
Cited
US4720812A
Cited
US5021996A
Cited
EP0306962A2
Cited
EP0364743A1
Cited
EP0361525A2
Cited
GB2226433A
Cited
US5101490A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-04-25 | 1997-10-25 | 1998-04-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-04-25 | 2001-10-25 | 2002-04-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-04-25 | 2005-10-25 | 2006-04-26 | $7700.00 | Window Closed / Lapsed |