Voltage controlled oscillator including voltage controlled delay circuit with power supply noise isolation

Claim 2

A voltage controlled delay circuit with power supply noise isolation, comprising: delay means responsive to an input voltage for varying the delay of a signal propagating through said delay means, and a transistor having a drain connected to a power supply, a gate connected to a control voltage, and a source providing said input voltage to said delay means such that said input voltage follows said control voltage and is isolated from noise on said power supply connection to said transistor.

Claim 3

The voltage controlled delay circuit as recited in claim 1, wherein said transistor comprises an n-mos transistor having a drain connected to a high voltage end of said power supply, a gate connected to said control voltage, and a source providing said input voltage to said delay means such that said input voltage follows said control voltage and is isolated from noise on said power supply connection to said n-mos transistor.

Claim 4

The voltage controlled delay circuit as recited in claim 1, wherein said transistor comprises a p-mos transistor having a drain connected to a low voltage end of said power supply, a gate connected to said control voltage, and a source providing said input voltage to said delay means such that said input voltage follows said control voltage and is isolated from noise on said power supply connection to said p-mos transistor.

Claim 5

The voltage controlled delay circuit as recited in claim 1, wherein said delay means comprises: a p-mos transistor having a source, a drain, and a gate, said p-mos transistor source connected to said input voltage, a capacitor having first and second ends, said second end connected to a low reference voltage, and an n-mos transistor having a source connected to said low reference voltage, a drain connected at an output node to said p-mos transistor drain and to said first end of said capacitor, and a gate connected at an input node to said p-mos transistor gate, such that varying said input voltage varies the delay of a signal propagating from said input node to said output node.

Claim 6

A voltage controlled delay circuit with power supply noise isolation, comprising: delay means responsive to an input voltage for varying the delay of a pair of signals propagating through said delay means, and a transistor having a drain connected to a power supply, a gate connected to a control voltage, and a source providing said input voltage to said delay means such that said input voltage follows said control voltage and is isolated from noise on said power supply connection to said transistor.

Claim 7

A voltage controlled delay circuit with power supply noise isolation, comprising: delay means responsive to an input voltage for varying the delay of a pair of signals propagating through said delay means, and a transistor having a drain connected to a power supply, a gate connected to a control voltage, and a source providing said input voltage to said delay means such that said input voltage follows said control voltage and is isolated from noise on said power supply connection to said transistor.

Claim 8

The voltage controlled delay circuit as recited in claim 5, wherein said transistor comprises a first n-mos transistor having a drain connected to a high voltage end of said power supply, a gate connected to said control voltage, and a source providing said input voltage to said delay means such that said input voltage follows said control voltage and is isolated from noise on said power supply connection to said first n-mos transistor.

Claim 9

The voltage controlled delay circuit as recited in claim 6, said delay means receiving first and second of said pair of signals respectively at first and second inputs of said delay means, and providing delayed versions of said first and second of said pair of signals respectively at second and first outputs of said delay means, wherein said delay means comprises: second and third n-mos transistors individually having a source, a drain, and a gate, said second and third n-mos transistor sources connected together and to said input voltage, said second and third n-mos transistor gates connected together and to said input voltage, and fourth and fifth n-mos transistors individually having a source, a drain, and a gate, said fourth and fifth n-mos transistor sources connected together and to a low reference voltage, said fourth n-mos transistor drain connected to said second n-mos transistor drain to form said first output of said delay means, said fifth n-mos transistor drain connected to said third n-mos transistor drain to form said second output of said delay means, and said fourth and fifth n-mos transistor gates respectively acting as said first and second inputs of said delay means.

Claim 10

The voltage controlled delay circuit as recited in claim 6, said delay means receiving first and second of said pair of signals respectively at first and second inputs of said delay means, and providing delayed versions of said first and second of said pair of signals respectively at second and first outputs of said delay means, wherein said delay means comprises: first and second p-mos transistors individually having a source, a drain, and a gate, said first and second p-mos transistor sources connected together and to said input voltage, said first p-mos transistor gate connected to said second p-mos transistor drain, and said second p-mos transistor gate connected to said first p-mos transistor drain, and second and third n-mos transistors individually having a source, a drain, and a gate, said second and third n-mos transistor sources connected together and to a low reference voltage, said second n-mos transistor drain connected to said first p-mos transistor drain to form said first output of said delay means, said third n-mos transistor drain connected to said second p-mos transistor drain to form said second output of said delay means, and said second and third n-mos transistor gates respectively acting as said first and second inputs of said delay means.

Claim 11

The voltage controlled delay circuit as recited in claim 8 further comprising a pair of clipping diodes connected between said first and second outputs of said delay means.

Claim 12

The voltage controlled delay circuit as recited in claim 5, wherein said transistor comprises a first p-mos transistor having a drain connected to a low voltage end of said power supply, a gate connected to said control voltage, and a source providing said input voltage to said delay means such that said input voltage follows said control voltage and is isolated from noise on said power supply connection to said first p-mos transistor.

Claim 13

The voltage controlled delay circuit as recited in claim 10, said delay means receiving first and second of said pair of signals respectively at first and second inputs of said delay means, and providing delayed versions of said first and second of said pair of signals respectively at second and first outputs of said delay means, wherein said delay means comprises: second and third p-mos transistors individually having a source, a drain, and a gate, said second and third p-mos transistor sources connected together and to a high reference voltage, and said second and third p-mos transistor gates respectively acting as said first and second inputs of said delay means, and fourth and fifth p-mos transistors individually having a source, a drain, and a gate, said fourth and fifth p-mos transistor sources connected together and to said input voltage, said fourth and fifth p-mos transistor gates connected together and to said input voltage, said fourth p-mos transistor drain connected to said second p-mos transistor drain to form said first output of said delay means, and said fifth p-mos transistor drain connected to said third p-mos transistor drain to form said second output of said delay means.

Claim 14

The voltage controlled delay circuit as recited in claim 10, said delay means receiving first and second of said pair of signals respectively at first and second inputs of said delay means, and providing delayed versions of said first and second of said pair of signals respectively at second and first outputs of said delay means, wherein said delay means comprises: second and third p-mos transistors individually having a source, a drain, and a gate, said second and third p-mos transistor sources connected together and to a high reference voltage, said second and third p-mos transistor gates respectively acting as said second and third inputs of said delay means, and first and second n-mos transistors individually having a source, a drain, and a gate, said first and second n-mos transistor sources connected together and to said input voltage, said first n-mos transistor gate connected to said second n-mos transistor drain and said third p-mos transistor drain to form said second output of said delay means, said second n-mos transistor gate connected to said first n-mos transistor drain and said second p-mos transistor drain to form said first output of said delay means.

Claim 15

The voltage controlled delay circuit as recited in claim 12 further comprising a pair of clipping diodes connected between said first and second outputs of said delay means.

Claim 16

In a voltage controlled oscillator, a ring oscillator comprising: a plurality of delay means responsive to an input voltage for varying the delay of a signal propagating through said delay means, and at least one transistor having a drain connected to a power supply, a gate connected to a control voltage, and a source providing said input voltage to said plurality of delay means such that said input voltage follows said control voltage and is isolated from noise on said power supply connection to said transistor.

Claim 17

In a voltage controlled oscillator, a ring oscillator comprising: a plurality of delay means responsive to an input voltage for varying the delay of a signal propagating through said delay means, and at least one transistor having a drain connected to a power supply, a gate connected to a control voltage, and a source providing said input voltage to said plurality of delay means such that said input voltage follows said control voltage and is isolated from noise on said power supply connection to said transistor.

Claim 18

The voltage controlled oscillator as recited in claim 14, wherein said at least one transistor comprises an n-mos transistor having a drain connected to a high voltage end of a power supply, a gate connected to said control voltage, and a source providing said input voltage to said plurality of delay means such that said input voltage follows said control voltage and is isolated from noise on said power supply connection to said n-mos transistor.

Claim 19

The voltage controlled oscillator as recited in claim 14, wherein said at least one transistor comprises a p-mos transistor having a drain connected to a low voltage end of a power supply, a gate connected to said control voltage, and a source providing said input voltage to said plurality of delay means such that said input voltage follows said control voltage and is isolated from noise on said power supply connection to said p-mos transistor.

Claim 20

In a voltage controlled oscillator, a plurality of voltage controlled delay circuits forming a ring oscillator, wherein at least one of said plurality of voltage controlled delay circuits comprises: delay means responsive to an input voltage for varying the delay of a pair of signals propagating through said delay means, and a transistor having a drain connected to a power supply, a gate connected to a control voltage, and a source providing said input voltage to said delay means such that said input voltage follows said control voltage and is isolated from noise on said power supply connection to said transistor.

Claim 21

In a voltage controlled oscillator, a plurality of voltage controlled delay circuits forming a ring oscillator, wherein at least one of said plurality of voltage controlled delay circuits comprises: delay means responsive to an input voltage for varying the delay of a pair of signals propagating through said delay means, and a transistor having a drain connected to a power supply, a gate connected to a control voltage, and a source providing said input voltage to said delay means such that said input voltage follows said control voltage and is isolated from noise on said power supply connection to said transistor.

Claim 22

The voltage controlled oscillator as recited in claim 17, wherein individual ones of said plurality of voltage controlled delay circuits comprises: delay means responsive to an input voltage for varying the delay of a pair of signals propagating through said delay means, and a transistor having a drain connected to a power supply, a gate connected to a control voltage, and a source providing said input voltage to said delay means such that said input voltage follows said control voltage and is isolated from noise on said power supply connection to said transistor.

Claim 23

A voltage controlled oscillator with power supply noise isolation comprising a plurality of pairs individually including a transistor and a voltage controlled delay cell, wherein individual ones of said transistors have a gate connected to a control voltage, a drain connected to a power supply, and a source connected to a voltage controlled delay cell paired to said individual one transistor for providing an input voltage to said voltage controlled delay cell such that said input voltage follows said control voltage and is isolated from noise on said power supply connection to said individual one transistor.

Claim 24

A voltage controlled oscillator with power supply noise isolation comprising a plurality of pairs individually including a transistor and a voltage controlled delay cell, wherein individual ones of said transistors have a gate connected to a control voltage, a drain connected to a power supply, and a source connected to a voltage controlled delay cell paired to said individual one transistor for providing an input voltage to said voltage controlled delay cell such that said input voltage follows said control voltage and is isolated from noise on said power supply connection to said individual one transistor.

Claim 25

The voltage controlled oscillator as recited in claim 19, wherein said voltage controlled delay circuits form a ring oscillator circuit.

Claim 26

A computer system comprising: a host processor; and a peripheral controller including a voltage controlled oscillator having at least one voltage controlled delay circuit with power supply noise isolation, wherein individual ones of said at least one voltage controlled delay circuit comprises a delay means responsive to an input voltage for varying the delay of a signal propagating through said delay means, and a transistor having a drain connected to a power supply, a gate connected to a control voltage, and a source providing said input voltage to said delay means such that said input voltage follows said control voltage and is isolated from noise on said power supply connection to said transistor.

Claim 27

A computer system comprising: a host processor; and a peripheral controller including a voltage controlled oscillator having at least one voltage controlled delay circuit with power supply noise isolation, wherein individual ones of said at least one voltage controlled delay circuit comprises a delay means responsive to an input voltage for varying the delay of a signal propagating through said delay means, and a transistor having a drain connected to a power supply, a gate connected to a control voltage, and a source providing said input voltage to said delay means such that said input voltage follows said control voltage and is isolated from noise on said power supply connection to said transistor.

Claim 28

The computer system as recited in claim 21, wherein said transistor comprises an n-mos transistor having a drain connected to a high voltage end of said power supply, a gate connected to said control voltage, and a source providing said input voltage to said delay means such that said input voltage follows said control voltage and is isolated from noise on said power supply connection to said n-mos transistor.

Claim 29

The computer system as recited in claim 21, wherein said transistor comprises a p-mos transistor having a drain connected to a low voltage end of said power supply, a gate connected to said control voltage, and a source providing said input voltage to said delay means such that said input voltage follows said control voltage and is isolated from noise on said power supply connection to said p-mos transistor.