US5557743A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Protection circuit for a microprocessor
Assignee: Motorola Mobility LLC
•
Filing: 1994-04-05
•
Granted: 1996-09-17
•
Expires: 2014-04-05
Abstract
Abstract Electronic devices using microprocessors requiring additional external memory can have security protection for the microprocessors while in an expanded mode of operation. A microprocessor having a security access circuit allows executable code to be stored in a peripheral storage device, such as external EPROM, while maintaining protection to the microprocessor EEPROM by monitoring if an instruction code is generated from an internal memory source or an external memory source.
Inventors
- 👤 Raul Pombo
- 👤 Jaime Borras
- 👤 Michel Bron
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 05:47
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/14; G06F12/1416; G06F12/1425; G06F12/1433; G11; G11C; G11C8/00; G11C8/20
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
124 words
A method for protecting an internal EEPROM of a microprocessor, the microprocessor having an address bus and a data bus configured for coupling an external memory to the microprocessor, the microprocessor acting upon an instruction originating from either internal memory, or external memory, the method comprising the steps of: determining if the instruction originates from the external memory or the internal memory; determining if the instruction originating from internal memory further originates from a read only memory; allowing access to the internal EEPROM, freezing the address bus to the external memory and floating the data bus to the external memory when the instruction originates from an internal read only memory; and disallowing access to the EEPROM when the instruction originates from the external memory.
Claim 2
Independent Claim
124 words
A method for protecting an internal EEPROM of a microprocessor, the microprocessor having an address bus and a data bus configured for coupling an external memory to the microprocessor, the microprocessor acting upon an instruction originating from either internal memory, or external memory, the method comprising the steps of: determining if the instruction originates from the external memory or the internal memory; determining if the instruction originating from internal memory further originates from a read only memory; allowing access to the internal EEPROM, freezing the address bus to the external memory and floating the data bus to the external memory when the instruction originates from an internal read only memory; and disallowing access to the EEPROM when the instruction originates from the external memory.
References Cited (Backward Citations)
US4211919A
Cited
JPS5694451A
Cited
JPS5745636A
Cited
US4590552A
Cited
JPS6341163A
Cited
JPS6376095A
Cited
US4958276A
Cited
JPS63163929A
Cited
US5012410A
Cited
US5134700A
Cited
US5305460A
Cited
US5278962A
Cited
US5168559A
Cited
US5014191A
Cited
JPH0219149A
Cited
JPH03135641A
Cited
US5210841A
Cited
US5379443A
Cited
US5247621A
Cited
US5404547A
Cited
JPH0546473A
Cited
JPH0612321A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-09-17 | 2000-03-18 | 2000-09-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-09-17 | 2004-03-18 | 2004-09-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-09-17 | 2008-03-18 | 2008-09-17 | $7700.00 | Window Closed / Lapsed |