Microprocessor providing encoded information on byte enable lines indicating whether reading code or data, location of code/data on data lines, and bit width of code/data

Claim 2

In a processor having a plurality of external data signal lines, a plurality of external byte enable signal lines, and an external read/write line which indicates whether the processor is in a read cycle or in a write cycle, a method for providing information to components external to said processor about reads and writes made by said processor, said method comprising the steps of: checking a state of said read/write line to determine whether the processor is making a read from or a write to an external memory; if said read write/line indicates a read cycle, determining internally within said processor whether said processor is making a read of code or a read of data; when said read/write signal line indicates a write cycle said processor providing byte enable signals on said byte enable signal lines, said byte enable signals indicating which of said data signal line contain valid signals; when said read/write signal line indicates a read cycle and said determination indicates a read of code, said processor providing predetermined first bit patterns on said byte enable signal lines, wherein said first bit patterns are encoded signals indicating that code is sought, and a location of said code on said data signal lines; and when said read/write signal line indicates a read cycle and said determination indicates a read of data, said processor providing predetermined second bit patterns on said byte enable signal lines, wherein said second bit patterns are encoded signals indicating data is sought, a bit width of said sought data, and a location of said sought data on said data signal lines wherein said second bit patterns are different than said first bit patterns.

Claim 3

The method of claim 1 wherein the number of said plurality of byte enable signal lines is eight and the number of said plurality of data signal lines is sixty-four.

Claim 4

The method of claim 2 wherein one of said first bit patterns is: BE7=1, BE6=0, BE5=1, BE4=0, BE3=1, BE2=1, BE1=1, and BE0=1 for a code read in the upper 32-bits of said data signal lines.

Claim 5

The method of claim 2 wherein one of said first bit patterns is: BE7=1, BE6=1, BE5=1, BE4=1, BE3=1, BE2=0, BE1=1, and BE0=0 for a code read in the lower 32-bits of said data signal lines.

Claim 6

A processor which writes and reads code and data to and from an external memory comprising: a plurality of external byte enable signal lines; a plurality of external data signal lines; an external read/write signal line for indicating when said processor is in a read cycle or in a write cycle; a plurality of internal access type lines which indicate an allowable size of code or data; a plurality of internal lower order address lines which indicate a location of code or data on said external data signal lines; an internal code/data line for indicating whether code or data is being read from said external memory; and a circuit, wherein said circuit generates byte enable signals on said byte enable signal lines when said read/write line indicates write cycle, said byte enable signals indicating which of said data sign lines contain valid signals; said circuit generating predetermined first bit patterns on said byte enable signal lines when said read/write line indicates a read cycle and said code/data line indicates a code read, wherein said predetermined first bit patterns are encoded signals indicating that code is sought and a location of said code on said data signal lines; said circuit generating predetermined second bit patterns on said byte enable signal lines when said read/write line indicates a read cycle and said code/data line indicates a data read, wherein said predetermined second bit patterns are encoded signals indicating that data is sought, a bit width of said data, and a location of said data on said data signal lines wherein said second bit patterns are different than said first bit patterns; said circuit utilizing said code/data line, said internal access type lines, and said lower order address lines as inputs for generating said first and second predetermined bit patterns.

Claim 7

A processor which writes and reads code and data to and from an external memory comprising: a plurality of external byte enable signal lines; a plurality of external data signal lines; an external read/write signal line for indicating when said processor is in a read cycle or in a write cycle; a plurality of internal access type lines which indicate an allowable size of code or data; a plurality of internal lower order address lines which indicate a location of code or data on said external data signal lines; an internal code/data line for indicating whether code or data is being read from said external memory; and a circuit, wherein said circuit generates byte enable signals on said byte enable signal lines when said read/write line indicates write cycle, said byte enable signals indicating which of said data sign lines contain valid signals; said circuit generating predetermined first bit patterns on said byte enable signal lines when said read/write line indicates a read cycle and said code/data line indicates a code read, wherein said predetermined first bit patterns are encoded signals indicating that code is sought and a location of said code on said data signal lines; said circuit generating predetermined second bit patterns on said byte enable signal lines when said read/write line indicates a read cycle and said code/data line indicates a data read, wherein said predetermined second bit patterns are encoded signals indicating that data is sought, a bit width of said data, and a location of said data on said data signal lines wherein said second bit patterns are different than said first bit patterns; said circuit utilizing said code/data line, said internal access type lines, and said lower order address lines as inputs for generating said first and second predetermined bit patterns.

Claim 8

The processor of claim 5 wherein the number of said plurality of byte enable signal lines is eight, and the number of said data signal lines is sixty-four.

Claim 9

The processor of claim 6 wherein said second means provides a bit pattern on said byte enable signal lines of BE7=1, BE6=0, BE5=1, BE4=0, BE3=1, BE2=1, BE1=1, and BE0=1 for a code read in the upper 32-bits of said data signal lines.

Claim 10

The processor of claim 6 wherein said second means provides a bit pattern of BE7=1, BE6=1, BE5=1, BE4=1, BE3=1, BE2=0, BE1=1, and BE0=0 for a code read in the lower 32-bits of said data signal lines.