US4825438A
Expired / Lapsed
US
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Bus error detection employing parity verification
Assignee: Unisys Corp
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Filing: 1987-11-16
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Granted: 1989-04-25
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Expires: 2007-11-16
Abstract
Abstract A bus error detection system is used to detect binary bus error signals. The bus lines include an odd parity line and an even parity line. A clock means provides at least two clock signal phases. An activatable driver drives both of the odd and the even parity lines to the same predefined logic level each time a first clock signal phase occurs. A parity checker coupled to the drive checks during a second clock signal phase the parity of the binary signals which appeared on said bus lines during a preceding first clock signal phase. The driver then drives either the odd or the even parity lines to a predefined logic state according to the parity determined by the parity checker during the second clock signal phase. A verification circuit verifies that only one of the odd and the even parity lines has been driven to a predefined logic state during said second clock phase, and that of both the odd and the even parity lines have been driven during said first clock signal phase to the same predefined logic level.
Inventors
- 👤 Donald B. Bennett
- 👤 Lee T. Thorsrud
- 👤 Thomas W. Petschauer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 10:09
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4208; G06F13/4217; G06F11/00; G06F11/07; G06F11/0703; G06F11/0751; G06F11/08; G06F11/10; G06F13/14; G06F13/36; G06F13/368; G06F13/374; F; F02; F02B; F02B75/00; F02B75/02; F02B2075/022; F02B2075/025
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
223 words
A bus error detection system for detecting errors in binary bus signals comprising a bus having a plurality of lines each coupled to one of a plurality of digital means, said bus lines including an odd parity line and an even parity line, said system comprising clock means which provides at least two clock signal phases, wherein said digital means comprises activatable drive means for driving both of said odd and even parity lines to the same predefined logic level each time said first clock signal phase occurs, parity checking means coupled to said drive means for checking during a second clock signal phase the parity of the binary signals which appeared on said bus lines during a preceding first clock signal phase, and for activating said drive means for driving either said odd or said even parity lines to a predefined logic state according to the parity determined by said parity checking means during said second clock signal phase, and verification means constructed to normally verify that only one of said odd and even parity lines has been driven by said digital means to said predefined logic state during said second clock phase, and that both said odd and said even parity lines have been driven by said drive means during said first clock signal phase to the same predefined logic level.
Claim 2
Dependent Claim
223 words
A bus error detection system for detecting errors in binary bus signals comprising a bus having a plurality of lines each coupled to one of a plurality of digital means, said bus lines including an odd parity line and an even parity line, said system comprising clock means which provides at least two clock signal phases, wherein said digital means comprises activatable drive means for driving both of said odd and even parity lines to the same predefined logic level each time said first clock signal phase occurs, parity checking means coupled to said drive means for checking during a second clock signal phase the parity of the binary signals which appeared on said bus lines during a preceding first clock signal phase, and for activating said drive means for driving either said odd or said even parity lines to a predefined logic state according to the parity determined by said parity checking means during said second clock signal phase, and verification means constructed to normally verify that only one of said odd and even parity lines has been driven by said digital means to said predefined logic state during said second clock phase, and that both said odd and said even parity lines have been driven by said drive means during said first clock signal phase to the same predefined logic level.
Claim 3
Dependent Claim
50 words
A bus error detection system as claimed in claim 1 further comprising error correction means coupled to said verification means for replacing faulty bus lines, comprising switching means for switching a faulty bus line out of said bus and for replacing said faulty bus line with an adjoining bus line.
Claim 4
Dependent Claim
103 words
A bus error detection system as claimed in claim 2 wherein said switching means switches each higher ordered bus line above a faulty bus line with its next higher ordered bus line until the highest ordered non-parity bus line is reached, and then for replacing the said highest ordered non-parity bus line with one of said odd or even parity lines, and an error correction modification means for modifying the operation of said verification means so that it thereafter operates in accordance with a single odd or even bus line parity error detection scheme as long as said faulty bus line remains replaced.
Claim 5
Dependent Claim
51 words
A bus error detection system as claimed in claim 1 wherein said verification means comprises means for determining if any bus line is open, or if any bus line is stuck high, or if any bus line is stuck low, or if any two or more bus lines are shorted together.
Claim 6
Dependent Claim
50 words
A bus error detection system as claimed in claim 4 further comprising error correction means coupled to said verification means for replacing faulty bus lines, comprising switching means for switching a faulty bus linen out of said bus and for replacing said faulty bus line with an adjoining bus line.
Claim 7
Dependent Claim
102 words
A bus error detection system as claimed in claim 5 wherein said switching means switches each higher ordered bus line above faulty bus line with its next higher ordered bus line until the highest ordered non-parity bus line is reached, and then for replacing the said highest ordered non-parity bus line with one of said odd or even parity lines, and an error correction modification means for modifying the operation of said verification means so that it thereafter operates in accordance with a single odd or even bus line parity error detection scheme as long as said faulty bus line remains replaced.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-04-24 | 1992-10-24 | 1993-04-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-04-24 | 1996-10-24 | 1997-04-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-04-24 | 2000-10-24 | 2001-04-25 | $7700.00 | Window Closed / Lapsed |