US3715727A
Expired / Lapsed
US
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Control mechanism and bus for a data processing pooler system
Assignee: Honeywell Inc
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Filing: 1970-06-11
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Granted: 1973-02-06
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Expires: 1990-06-11
Abstract
Abstract An improved data processing pooler system for pooling data cooperatively to a central computer compatible magnetic tape or tapes from other computer compatible magnetic tape or tapes, utilizing key-to-tape units, each key-to-tape unit having devicecontrol-area (DCA) units as an interface between said key-to-tape units, said DCA''s being coupled to each other by a pooler bus of the ''''hand shake'''' type having a plurality of bidirectional lines for transmitting or receiving control and/or data signals. The system comprises input/output devices of the key-to-tape type, one device having a master pooler adapter and controls capable of operating as the master or control pooler unit, whereas the other devices have a slave pooler and controls capable of operating as slave or controlled pooler unit(s). An input/output (I/O) bus connects a central processor (CCU or CPU) unit in each key-totape unit with the device-control-area (DCA) also in each key-totape unit; said I/O bus contains a group of bi-directional multifunction lines, single function lines and a second group of control lines which form an array. Sending key-to-tape units and receiving key-to-tape units, each individually having its own memory, are connected by a pooler bus, and interfaced via the key-to-tape device-control areas (DCA''s) which contain the necessary logic to link the sending and receiving pooler adapters together, and to provide the control of information flow to and/or from the respective sending and receiving memories. Additional logic circuitry write and/or read information into or out of said memories and onto or out of the magnetic tapes.
Inventors
- 👤 F Yu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 04:44
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4221; G06F13/4226
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
156 words
A data processing system comprising: a. first and second central processor units (CPU''s), each of said first and second CPU''s having a buffer memory respectively; b. first and second peripheral control units (PCU''s); c. first and second input/output (I/O) buses coupling said first CPU to said first PCU, and said second CPU to said second PCU, respectively; d. a peripheral bus coupling said first and second PCU''s; e. first means coupled to said first and second I/O buses and to said pooler bus for asynchronously transmitting or receiving request and acknowledge signals between said PCU''s under control of said PCU''s; f. and second means coupled to said first and second I/O buses and to said pooler bus, said second means for asynchronously and bidirectionally transmitting or receiving parallel control and data signals simultaneously between said buffer memories in each of said CPU''s over said peripheral and first and second I/O buses, under control of said PCU''s.
Claim 2
Dependent Claim
156 words
A data processing system comprising: a. first and second central processor units (CPU''s), each of said first and second CPU''s having a buffer memory respectively; b. first and second peripheral control units (PCU''s); c. first and second input/output (I/O) buses coupling said first CPU to said first PCU, and said second CPU to said second PCU, respectively; d. a peripheral bus coupling said first and second PCU''s; e. first means coupled to said first and second I/O buses and to said pooler bus for asynchronously transmitting or receiving request and acknowledge signals between said PCU''s under control of said PCU''s; f. and second means coupled to said first and second I/O buses and to said pooler bus, said second means for asynchronously and bidirectionally transmitting or receiving parallel control and data signals simultaneously between said buffer memories in each of said CPU''s over said peripheral and first and second I/O buses, under control of said PCU''s.
Claim 3
Dependent Claim
156 words
A data processing system comprising: a. first and second central processor units (CPU''s), each of said first and second CPU''s having a buffer memory respectively; b. first and second peripheral control units (PCU''s); c. first and second input/output (I/O) buses coupling said first CPU to said first PCU, and said second CPU to said second PCU, respectively; d. a peripheral bus coupling said first and second PCU''s; e. first means coupled to said first and second I/O buses and to said pooler bus for asynchronously transmitting or receiving request and acknowledge signals between said PCU''s under control of said PCU''s; f. and second means coupled to said first and second I/O buses and to said pooler bus, said second means for asynchronously and bidirectionally transmitting or receiving parallel control and data signals simultaneously between said buffer memories in each of said CPU''s over said peripheral and first and second I/O buses, under control of said PCU''s.
Claim 4
Dependent Claim
156 words
A data processing system comprising: a. first and second central processor units (CPU''s), each of said first and second CPU''s having a buffer memory respectively; b. first and second peripheral control units (PCU''s); c. first and second input/output (I/O) buses coupling said first CPU to said first PCU, and said second CPU to said second PCU, respectively; d. a peripheral bus coupling said first and second PCU''s; e. first means coupled to said first and second I/O buses and to said pooler bus for asynchronously transmitting or receiving request and acknowledge signals between said PCU''s under control of said PCU''s; f. and second means coupled to said first and second I/O buses and to said pooler bus, said second means for asynchronously and bidirectionally transmitting or receiving parallel control and data signals simultaneously between said buffer memories in each of said CPU''s over said peripheral and first and second I/O buses, under control of said PCU''s.
Claim 5
Dependent Claim
59 words
A data processing system as recited in claim 1 including third and fourth means for asynchronously and bidirectionally transmitting control and data signals from said first CPU to said second PCU or from said second CPU to said second PCU over said first or second I/O bus, respectively, under control of signals from said first and second I/O buses.
Claim 6
Dependent Claim
158 words
A data processing system comprising: a. a plurality of central control units (CPU''s), each of said CPU''s having a buffer memory; b. a plurality of input/output buses coupled one each to one each of said central control units; c. a plurality of peripheral control units (PCU''s) coupled one each to one each of said input/output buses; d. a pooler bus coupled to said peripheral control units (PCU''s) for carrying information or control signals therebetween; e. first logic means coupled to said input/output buses and to said pooler bus for providing control signals for asynchronous transmission or reception of information or control signals between said buffer memories of said CPU''s, said information and/or control signals carried by said input/output and pooler buses; and f. second logic means coupled to said input/output buses and to said pooler bus for providing communication signals for asynchronously requesting and acknowledging information between said PCU''s, said second logic means under control of said PCU''s.
Claim 7
Dependent Claim
158 words
A data processing system comprising: a. a plurality of central control units (CPU''s), each of said CPU''s having a buffer memory; b. a plurality of input/output buses coupled one each to one each of said central control units; c. a plurality of peripheral control units (PCU''s) coupled one each to one each of said input/output buses; d. a pooler bus coupled to said peripheral control units (PCU''s) for carrying information or control signals therebetween; e. first logic means coupled to said input/output buses and to said pooler bus for providing control signals for asynchronous transmission or reception of information or control signals between said buffer memories of said CPU''s, said information and/or control signals carried by said input/output and pooler buses; and f. second logic means coupled to said input/output buses and to said pooler bus for providing communication signals for asynchronously requesting and acknowledging information between said PCU''s, said second logic means under control of said PCU''s.
Claim 8
Dependent Claim
60 words
A data processing system as recited in claim 3 including first selection means for enabling at least one of said peripheral control units (PCU''s) for transmission of information and control signals between said PCU''s and second selection means for enabling at least a second of said peripheral control units (PCU''s) for reception of information and control signals between said PCU''s.
Claim 9
Dependent Claim
34 words
A data processing system as recited in claim 4 wherein said peripheral devices are key-to-tape units wherein one peripheral device comprises a master key-to-tape unit and the other peripheral devices comprise slave key-to-tape units.
Claim 10
Dependent Claim
22 words
A data processing system as recited in claim 3 wherein said logic means include synchronous timing means for providing synchronous timing signals.
Claim 11
Dependent Claim
50 words
A data processing system as recited in claim 6 wherein said logic means further include asynchronous timing means for providing asynchronous timing signals, said asynchronous signals asynchronously timing the processing of the information carried by said I/O and pooler buses, and the synchronous timing signals synchronously clocking said asynchronous signals.
Claim 12
Dependent Claim
42 words
A data processing system as recited in claim 7 wherein said logic means further include holding means for holding the information signals carried on said pooler bus on said pooler bus until released by release means responsive to said synchronous timing signals.
Claim 13
Dependent Claim
243 words
A data processing system comprising: a. at least one transmitter central control unit and at least one receiver central control unit; b. at least one transmitter input device, and at least one receiver output device; c. a transmitter input/output bus and a receiver input/output bus each bus having its own plurality of parallel multifunction bidirectional and single function bidirectional lines; d. first logic means in said transmitter central control unit for generating a plurality of traffic states, said first logic means coupling said transmitter input/output bus to said transmitter control unit; e. a second logic means in said receiver central control unit for generating a plurality of traffic states, said second logic mEans coupling said receiver input/output bus to said receiver central control unit; f. third logic means coupling said transmitter input device to said transmitter input/output bus, said third logic means being responsive to one or more of the traffic states generated by said first logic means; g. fourth logic means coupling said receiver input/output bus, said fourth logic means being responsive to one or more of the traffic states generated by said second logic means; and h. a pooler bus having its own plurality of parallel bidirectional lines, said pooler bus coupled to said third and fourth logic means, and said pooler bus being responsive to said third and fourth logic means for transmitting substantially simultaneously and in parallel, data signals from said transmitter input/output bus to said receiver input/output bus.
Claim 14
Dependent Claim
243 words
A data processing system comprising: a. at least one transmitter central control unit and at least one receiver central control unit; b. at least one transmitter input device, and at least one receiver output device; c. a transmitter input/output bus and a receiver input/output bus each bus having its own plurality of parallel multifunction bidirectional and single function bidirectional lines; d. first logic means in said transmitter central control unit for generating a plurality of traffic states, said first logic means coupling said transmitter input/output bus to said transmitter control unit; e. a second logic means in said receiver central control unit for generating a plurality of traffic states, said second logic mEans coupling said receiver input/output bus to said receiver central control unit; f. third logic means coupling said transmitter input device to said transmitter input/output bus, said third logic means being responsive to one or more of the traffic states generated by said first logic means; g. fourth logic means coupling said receiver input/output bus, said fourth logic means being responsive to one or more of the traffic states generated by said second logic means; and h. a pooler bus having its own plurality of parallel bidirectional lines, said pooler bus coupled to said third and fourth logic means, and said pooler bus being responsive to said third and fourth logic means for transmitting substantially simultaneously and in parallel, data signals from said transmitter input/output bus to said receiver input/output bus.
Claim 15
Dependent Claim
33 words
A data processing system as recited in claim 9 wherein said plurality of lines of said pooler bus comprise at least two groups of lines, said groups being data lines and control lines.
Claim 16
Dependent Claim
53 words
A data processing system as recited in claim 10 wherein said plurality of lines of each of said receiver and transmitter input/output buses comprises two groups of lines, said two groups of lines of said receiver and transmitter input/output buses being parallel bidirectional single function control lines and parallel bidirectional multi-function data lines.
Claim 17
Dependent Claim
53 words
A data processing system as recited in claim 9 wherein said traffic states generated by said first and second logic means are four in number, traffic states 1, 2, 3 and 4, and wherein traffic states 1 and 2 are essentially input states, and traffic states 3 and 4 are essentially output states.
Claim 18
Dependent Claim
83 words
A data processing system as recited in claim 12 including a first and second record size memory unit in said transmitter and receiver central control units, respectively, wherein data is entered into said first memory unit during traffic state 1 of said transmitter and transmitted to said second memory unit during traffic state 4 of said transmitter and traffic state 2 of said receiver and wherein data is released from said second memory unit for recording during traffic state 4 of said receiver.
Claim 19
Dependent Claim
103 words
A data processing system as recited in claim 13 wherein said transmitter central control units and said transmitter input device and said receiver central control units and said receiver output device comprise in combination transmitter and receiver key-to-tape devices, respectively, each of said key-to-tape devices having mounted thereon computer compatible magnetic tape, and each of said transmitter key-to-tape devices including means for reading data from the magnetic tape mounted thereon into said first record size memory unit, and each receiver key-to-tape device including means for writing data from said second record size memory onto the magnetic tape mounted on said receiver key-to-tape device.
Claim 20
Dependent Claim
65 words
A data processing system as recited in claim 9 including first selection means for enabling selected ones of said transmitter central control units for parallel transmission of information or control signals carried by said transmitter input-output bus, and second selection means for enabling selected ones of said receiver central control units for parallel reception of information or control signals carried by said receiver input/output bus.
Claim 21
Dependent Claim
211 words
An input/output control system comprising: a. I/O bus means having a plurality of parallel multi-function and single function bidirectional lines for the parallel transmission or reception of data signals on selected ones of said parallel bidirectional multi-function lines of said I/O bus means under control of signals on said parallel bidirectional signal function lines of said I/O bus means; b. pooler bus means having a plurality of parallel bidirectional lines for the parallel transmission or reception of data on selected ones of said parallel bidirectIonal lines of said pooler bus means under control of signals on said single function bidirectional lines of said I/O bus means; c. a traffic controller coupled to said I/O bus means and pooler bus means for sequentially establishing a plurality of traffic states; d. first means responsive to said traffic states for establishing signals for controlling the parallel flow of information in response to said traffic states said first means coupled to said I/O and pooler bus means; e. second means coupled to said I/O and pooler bus means for placing information and control signals on said I/O and pooler bus means; f. and third means coupled to said I/O and pooler bus means for removing information and control signals from said I/O and pooler buses.
Claim 22
Dependent Claim
211 words
An input/output control system comprising: a. I/O bus means having a plurality of parallel multi-function and single function bidirectional lines for the parallel transmission or reception of data signals on selected ones of said parallel bidirectional multi-function lines of said I/O bus means under control of signals on said parallel bidirectional signal function lines of said I/O bus means; b. pooler bus means having a plurality of parallel bidirectional lines for the parallel transmission or reception of data on selected ones of said parallel bidirectIonal lines of said pooler bus means under control of signals on said single function bidirectional lines of said I/O bus means; c. a traffic controller coupled to said I/O bus means and pooler bus means for sequentially establishing a plurality of traffic states; d. first means responsive to said traffic states for establishing signals for controlling the parallel flow of information in response to said traffic states said first means coupled to said I/O and pooler bus means; e. second means coupled to said I/O and pooler bus means for placing information and control signals on said I/O and pooler bus means; f. and third means coupled to said I/O and pooler bus means for removing information and control signals from said I/O and pooler buses.
Claim 23
Dependent Claim
60 words
An input/output control device as recited in claim 16 wherein said I/O bus means comprises an array of control and signal lines in columns and rows, respectively, and said pooler bus means comprises d bidirectional data lines and c bidirectional control lines where d is the number of bidirectional data lines and c is the number of bidirectional control lines.
Claim 24
Dependent Claim
21 words
An input/output control device as recited in claim 17 wherein d is equal to 9 and c is equal to 16.
Claim 25
Dependent Claim
135 words
In combination with a data processing pooling system comprising a master central control unit (CCU) and a slave central control unit, a plurality of input-output buses coupled to said master and slave control units, a master device control area (DCA) and a slave device control area (DCA) coupled to said input-output buses, and a pooler bus coupled to said master and slave DCA''s: a. unit-defined-logic means and said master and slave (DCA''s) for generating address valid signals in response to signals from said master and slave central control units, said address valid signals for notifying the master (CCU) that the slave (CCU) is initialized to receive information from the master (CCU); and, b. A master and slave (DCA) timing logic means for generating sequential DCA timing pulses for sequentially initiating the generation of control signals.
Claim 26
Dependent Claim
135 words
In combination with a data processing pooling system comprising a master central control unit (CCU) and a slave central control unit, a plurality of input-output buses coupled to said master and slave control units, a master device control area (DCA) and a slave device control area (DCA) coupled to said input-output buses, and a pooler bus coupled to said master and slave DCA''s: a. unit-defined-logic means and said master and slave (DCA''s) for generating address valid signals in response to signals from said master and slave central control units, said address valid signals for notifying the master (CCU) that the slave (CCU) is initialized to receive information from the master (CCU); and, b. A master and slave (DCA) timing logic means for generating sequential DCA timing pulses for sequentially initiating the generation of control signals.
Claim 27
Dependent Claim
23 words
The combination as recited in claim 19 wherein the number of sequential timing pulses generated in each DCA timing logic means is four.
Claim 28
Dependent Claim
46 words
The combination as recited in claim 20 including means responsive to the sequential DCA timing pulses for generating request and acknowledge signals from said master and slave DCA''s to said master and slave central control units CCU''s, and for generating signals for resetting said unit-defined-logic means.
Claim 29
Dependent Claim
266 words
In a data processing pooler system comprising at least a master and a slave central control unit (CCU) each having a traffic controller and record memory, a master and slave device control area (DCA), a master I/O bus coupling said master CCU and master DCA, and a slave I/O bus coupling said slave CCU and slave DCA, and a pooler bus coupling said master and slave DCA''s: a. first means coupled to said master record memory, said first means for reading information out of said master record memory and a first auxiliary means coupled to said master record memory and said master I/O bus, said first auxiliary means for placing the information on said master I/O bus; b. second means coupled to said master I/O bus and to said master DCA, said second means for gating the information from said master I/O bus to said master DCA; c. third means coupled to said master DCA and to said pooler bus, said third means for gating the information from said master DCA to said pooler bus; d. fourth means coupled to said pooler bus and to said slave DCA, said fourth means for gating the information from said pooler bus to said slave DCA; e. fifth means coupled to said slave DCA and to said slave I/O bus, said fifth means for placing the information from said slave DCA on said slave I/O bus; f. and sixth means coupled to said slave I/O bus and to said slave record memory, said sixth means for writing the information from said slave I/O bus into said slave record memory.
Claim 30
Dependent Claim
266 words
In a data processing pooler system comprising at least a master and a slave central control unit (CCU) each having a traffic controller and record memory, a master and slave device control area (DCA), a master I/O bus coupling said master CCU and master DCA, and a slave I/O bus coupling said slave CCU and slave DCA, and a pooler bus coupling said master and slave DCA''s: a. first means coupled to said master record memory, said first means for reading information out of said master record memory and a first auxiliary means coupled to said master record memory and said master I/O bus, said first auxiliary means for placing the information on said master I/O bus; b. second means coupled to said master I/O bus and to said master DCA, said second means for gating the information from said master I/O bus to said master DCA; c. third means coupled to said master DCA and to said pooler bus, said third means for gating the information from said master DCA to said pooler bus; d. fourth means coupled to said pooler bus and to said slave DCA, said fourth means for gating the information from said pooler bus to said slave DCA; e. fifth means coupled to said slave DCA and to said slave I/O bus, said fifth means for placing the information from said slave DCA on said slave I/O bus; f. and sixth means coupled to said slave I/O bus and to said slave record memory, said sixth means for writing the information from said slave I/O bus into said slave record memory.
Claim 31
Dependent Claim
20 words
The data processing pooler system as recited in claim 22 wherein said second, third and fourth means comprise AND gates.
Claim 32
Dependent Claim
83 words
A data processing pooler system comprising a plurality of key-to-tape devices each having a central control unit (CCU); a plurality of I/O buses coupled one each to one each of said CCU''s; a pooler bus coupled to each CCU; device selection means coupled to said CCU''s, said device selection means for designating a master key-to-tape-unit, said master key-to-tape unit for transmitting information to the other of said plurality of key-to-tape devices, said device selection means including device enabling means for enabling a select-read-function.
Claim 33
Dependent Claim
83 words
A data processing pooler system comprising a plurality of key-to-tape devices each having a central control unit (CCU); a plurality of I/O buses coupled one each to one each of said CCU''s; a pooler bus coupled to each CCU; device selection means coupled to said CCU''s, said device selection means for designating a master key-to-tape-unit, said master key-to-tape unit for transmitting information to the other of said plurality of key-to-tape devices, said device selection means including device enabling means for enabling a select-read-function.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1976-02-06 | 1976-08-07 | 1977-02-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1980-02-06 | 1980-08-07 | 1981-02-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1984-02-06 | 1984-08-07 | 1985-02-06 | $7700.00 | Window Closed / Lapsed |