Patent US5554940A successfully refreshed from Google Patents.
US5554940A
Expired / Lapsed
US
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Bumped semiconductor device and method for probing the same
Assignee: NXP USA Inc
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Filing: 1994-07-05
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Granted: 1996-09-10
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Expires: 2014-07-05
Abstract
Abstract Probing array bumped semiconductor devices using cantilever probe needles is facilitated by the formation of peripheral test pads. A semiconductor die (10) includes bond pads (12). A redistribution metallization layer is deposited and patterned to form individual redistribution structures (26) associated with and electrically coupled to each bond pad. Each redistribution structure includes a test pad (28), a bump pad (30) and a bump pad interconnect (32). The test pads are formed in positions close to those of the underlying bond pads, while the bump pads can be formed anywhere within the die. Having the test pads located similarly to the bond pads enables the same or a similar probe card apparatus and cantilever needles (50) to probe the die either at the bond pads for devices which are to be wire bonded or TAB bonded, or at the test pads for devices which are to be bumped.
Inventors
- 👤 Eric M. Hubacher
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 14:04
CPC Classifications
G; G01; G01R; G01R1/00; G01R1/02; G01R1/06; G01R1/067; G01R1/073; G01R1/07392; G01R1/07307; G01R1/07314; H; H10; H10W; H10W72/00; H10W72/90; H10W70/00; H10W70/60; H10W72/01; H10W72/019; H10W72/20; H10W72/29; H10W72/931; H10W72/932; H10W72/981; H10W72/983
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
174 words
A semiconductor device comprising: a semiconductor die having a semiconductor substrate with integrated circuitry formed thereon; the semiconductor die further comprising: a first metal layer overlying the semiconductor substrate and patterned to form a plurality of bond pads, the plurality of bond pads being electrically connected to the integrated circuitry; an insulating layer overlying the first metal layer, the insulating layer having a plurality of openings formed therein such that each opening exposes a portion of an underlying bond pad; a second metal layer overlying the insulating layer and filling the plurality of openings to form a plurality of contacts to the plurality of bond pads, the second metal layer being patterned to also form a plurality of test pads electrically connected to the plurality of contacts, a plurality of bump pads, and a plurality of interconnects, wherein each test pad is electrically connected to a corresponding one of the plurality of bump pads by one of the plurality of interconnects; and a plurality of conductive bumps formed on the plurality of bump pads.
Claim 2
Dependent Claim
174 words
A semiconductor device comprising: a semiconductor die having a semiconductor substrate with integrated circuitry formed thereon; the semiconductor die further comprising: a first metal layer overlying the semiconductor substrate and patterned to form a plurality of bond pads, the plurality of bond pads being electrically connected to the integrated circuitry; an insulating layer overlying the first metal layer, the insulating layer having a plurality of openings formed therein such that each opening exposes a portion of an underlying bond pad; a second metal layer overlying the insulating layer and filling the plurality of openings to form a plurality of contacts to the plurality of bond pads, the second metal layer being patterned to also form a plurality of test pads electrically connected to the plurality of contacts, a plurality of bump pads, and a plurality of interconnects, wherein each test pad is electrically connected to a corresponding one of the plurality of bump pads by one of the plurality of interconnects; and a plurality of conductive bumps formed on the plurality of bump pads.
Claim 3
Dependent Claim
27 words
The semiconductor device of claim 1 wherein at least one test pad overlies and at least partially overlaps a corresponding one of the plurality of bond pads.
Claim 4
Dependent Claim
34 words
The semiconductor device of claim 1 wherein a first bump pad of the plurality of bump pads is at least partially formed directly over a first bond pad of the plurality of bond pads.
Claim 5
Dependent Claim
83 words
The device of claim 1 wherein the plurality of bond pads comprises a first bond pad having an edge, wherein the plurality of test pads comprises a first test pad which corresponds with and overlies the first bond pad, the first test pad having an edge which corresponds with the edge of the first bond pad, and wherein a displacement distance between the edge of the first bond pad and the edge of the first test pad is less than approximately 0.25 mm.
Claim 6
Dependent Claim
28 words
The device of claim 1 wherein the semiconductor die has a periphery, and wherein the plurality of bond pads are formed around the periphery of the semiconductor die.
Claim 7
Dependent Claim
44 words
The device of claim 5 wherein the plurality of bump pads are formed at least partially in an array configuration within the periphery, and wherein one of the plurality of the bump pads is at least three bump pads deep in the array configuration.
Claim 8
Independent Claim
17 words
The device of claim I wherein the plurality of conductive bumps comprises a plurality of solder bumps.
Claim 9
Dependent Claim
112 words
A semiconductor device comprising: a semiconductor die having integrated circuitry formed thereon; the semiconductor die further comprising: a bond pad electrically connected to a portion of the integrated circuitry; an insulating layer overlying the bond pad; an opening in the insulating layer which exposes a portion of the bond pad; a metal contact formed in the opening and making electrical connection to the bond pad; a test pad formed over the insulating layer and electrically connected to the metal contact; a bump pad for receiving a conductive bump formed over the insulating layer; and a metal interconnect formed over the insulating layer and electrically connecting the test pad and the bump pad.
Claim 10
Dependent Claim
112 words
A semiconductor device comprising: a semiconductor die having integrated circuitry formed thereon; the semiconductor die further comprising: a bond pad electrically connected to a portion of the integrated circuitry; an insulating layer overlying the bond pad; an opening in the insulating layer which exposes a portion of the bond pad; a metal contact formed in the opening and making electrical connection to the bond pad; a test pad formed over the insulating layer and electrically connected to the metal contact; a bump pad for receiving a conductive bump formed over the insulating layer; and a metal interconnect formed over the insulating layer and electrically connecting the test pad and the bump pad.
Claim 11
Dependent Claim
18 words
The device of claim 8 wherein the test pad overlies and at least partially overlaps the bond pad.
Claim 12
Dependent Claim
18 words
The device of claim 8 wherein the bump pad overlies and at least partially overlaps the bond pad.
Claim 13
Dependent Claim
36 words
The device of claim 8 wherein the semiconductor die has a periphery, wherein the bond pad is formed adjacent the periphery, and wherein the bump pad is positioned farther from the periphery than the bond pad.
Claim 14
Dependent Claim
16 words
The device of claim 8 further comprising a conductive solder bump formed on the bump pad.
Claim 15
Dependent Claim
21 words
The device of claim 12 further comprising barrier metal formed on the bump pad without being formed on the test pad.
Claim 16
Dependent Claim
34 words
The device of claim 8 wherein the bond pad is formed from a first metal layer and the test pad, the bump pad, and the metal interconnect are formed from a second metal layer.
Claim 17
Independent Claim
178 words
A method for probing a semiconductor device comprising the steps of: providing a semiconductor substrate having integrated circuitry formed thereon within a defined semiconductor die area which is to be tested; forming a plurality of bond pads overlying the semiconductor substrate within the defined semiconductor die area and electrically connected to the integrated circuitry; depositing an insulating layer over the plurality of bond pads; forming a plurality of openings in the insulating layer such that an opening overlies each bond pad to expose a portion thereof; depositing a metal layer over the insulating layer and into the plurality of openings such that the metal layer is in electrical contact with the plurality of bond pads; patterning the metal layer to form a redistribution metal structure associated with each bond pad, the redistribution metal structure of each associated bond pad comprising: a test pad electrically connected to the associated bond pad; a bump pad; and a metal interconnect which electrically connects the test pad and bump pad; and probing each test pad to test functionality of the integrated circuitry.
Claim 18
Independent Claim
178 words
A method for probing a semiconductor device comprising the steps of: providing a semiconductor substrate having integrated circuitry formed thereon within a defined semiconductor die area which is to be tested; forming a plurality of bond pads overlying the semiconductor substrate within the defined semiconductor die area and electrically connected to the integrated circuitry; depositing an insulating layer over the plurality of bond pads; forming a plurality of openings in the insulating layer such that an opening overlies each bond pad to expose a portion thereof; depositing a metal layer over the insulating layer and into the plurality of openings such that the metal layer is in electrical contact with the plurality of bond pads; patterning the metal layer to form a redistribution metal structure associated with each bond pad, the redistribution metal structure of each associated bond pad comprising: a test pad electrically connected to the associated bond pad; a bump pad; and a metal interconnect which electrically connects the test pad and bump pad; and probing each test pad to test functionality of the integrated circuitry.
Claim 19
Dependent Claim
59 words
The method of claim 15 wherein the step of forming a plurality of bond pads comprises forming a plurality of bond pads along a periphery of the defined semiconductor die area, and wherein the step of patterning comprises patterning the metal layer such that each test pad is also formed along the periphery of the defined semiconductor die area.
Claim 20
Dependent Claim
16 words
The method of claim 15 wherein the step of probing comprises probing using cantilever probe needles.
Claim 21
Dependent Claim
18 words
The method of claim 15 further comprising the step of forming a conductive bump on each bump pad.
Claim 22
Dependent Claim
33 words
The method of claim 18 further comprising the step of depositing a barrier metal on each bump pad, prior to forming the conductive bump, and without depositing barrier metal on any test pad.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-09-10 | 2000-03-11 | 2000-09-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-09-10 | 2004-03-11 | 2004-09-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-09-10 | 2008-03-11 | 2008-09-10 | $7700.00 | Window Closed / Lapsed |