Patent US5553067A successfully refreshed from Google Patents.
US5553067A
Expired / Lapsed
US
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Generation of checking data
Assignee: STMicroelectronics Ltd Great Britain
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Filing: 1994-10-07
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Granted: 1996-09-03
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Expires: 2014-10-07
Abstract
Abstract A scheme for altering checking information in a message packet intended to be transmitted between computers is described. In this scheme, when an information portion of the packet is altered, checking bits contained in the packets are altered in dependence only on the set of checking bits in the message packet before modification of the information portion and on the modifications to the information portion. Thus, it is not necessary to generate new checking bits from a modified information portion.
Inventors
- 👤 Christopher P. H. Walker
- 👤 Peter W. Thompson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 17:38
CPC Classifications
H; H04; H04L; H04L1/00; H04L1/0078; H04L1/0083; H03; H03M; H03M13/00; H03M13/03; H03M13/05; H03M13/09; H03M13/093
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
113 words
A method of modifying a message packet which comprises a plurality of sets of information bits constituting an information portion and a set of checking bits, all sets containing the same number of bits in a sequence of bit locations between a bit location of least significance to a bit location of most significance, and each checking bit having been generated by taking the logical sum of bits having the same significance in all of the sets, the method comprising: modifying the information portion of said message packet; and altering the checking bits by using only the set of checking bits in the unmodified message packet and the modifications to the information portion.
Claim 2
Independent Claim
113 words
A method of modifying a message packet which comprises a plurality of sets of information bits constituting an information portion and a set of checking bits, all sets containing the same number of bits in a sequence of bit locations between a bit location of least significance to a bit location of most significance, and each checking bit having been generated by taking the logical sum of bits having the same significance in all of the sets, the method comprising: modifying the information portion of said message packet; and altering the checking bits by using only the set of checking bits in the unmodified message packet and the modifications to the information portion.
Claim 3
Dependent Claim
57 words
A method according to claim 1 wherein the step of modifying the information portion comprises inverting at least one information bit in a place of certain significance within a set of bits and wherein the step of altering the checking bits comprises inverting the bit in the place of same significance in the set of checking bits.
Claim 4
Dependent Claim
25 words
A method according to claim 2 wherein the message packet is arranged for serial transmission with the information portion preceding the set of checking bits.
Claim 5
Dependent Claim
35 words
A method according to claim 3 wherein the message packet includes a terminator portion following said information portion, said terminator portion including control information defining the end of packet and said set of checking bits.
Claim 6
Dependent Claim
25 words
A method according to claim 1 wherein the message packet is arranged for serial transmission with the information portion preceding the set of checking bits.
Claim 7
Dependent Claim
35 words
A method according to claim 5 wherein the message packet includes a terminator portion following said information portion, said terminator portion including control information defining the end of packet and said set of checking bits.
Claim 8
Dependent Claim
59 words
A method according to claim 1 wherein the step of modifying the information portion comprises adding or deleting a set of bits and wherein the step of altering the checking bits comprises taking the exclusive-OR of each bit within said added or deleted set with the bit in a place of corresponding significance within the set of checking bits.
Claim 9
Dependent Claim
25 words
A method according to claim 7 wherein the message packet is arranged for serial transmission with the information portion preceding the set of checking bits.
Claim 10
Dependent Claim
35 words
A method according to claim 8 wherein the message packet includes a terminator portion following said information portion, said terminator portion including control information defining the end of packet and said set of checking bits.
Claim 11
Dependent Claim
26 words
A method according to claim 1 wherein the information portion of said message packet includes a header portion comprising at least one set of address bits.
Claim 12
Dependent Claim
38 words
A method according to claim 10 wherein the header portion comprises a plurality of sets of address bits providing first and second headers and wherein said step of modifying the information portion comprises removing one of said headers.
Claim 13
Dependent Claim
12 words
A method according to claim 11 wherein each header is one byte.
Claim 14
Dependent Claim
44 words
A method according to claim 10 wherein the header portion comprises a plurality of sets of address bits providing first and second headers and wherein said step of modifying the information portion comprises adding at least one set of address bits to said packet.
Claim 15
Dependent Claim
26 words
A method according to claim 1 wherein the step of modifying the information portion includes adding at least one set of address bits to said packet.
Claim 16
Dependent Claim
14 words
A method according to claim 1 wherein each set of bits has four bits.
Claim 17
Dependent Claim
41 words
A method according to claim 1 wherein the information portion of said message packet includes a header portion comprising at least one set of address bits, wherein each set of bits has four bits and wherein each header is one byte.
Claim 18
Independent Claim
147 words
A method of transmitting a message packet between source and destination nodes via a network having a plurality of routing nodes, each message packet comprising a plurality of sets of information bits constituting an information portion and a set of checking bits, all sets containing the same number of bits in a sequence of bit locations between a bit location of least significance to a bit location of most significance, and each checking bit having been generated by taking the logical sum of bits having the same significance in all of the sets, wherein a method of modifying the message packet is effected at at least one node in the network, this method comprising: modifying the information portion of said message packet; and altering the checking bits by using only the set of checking bits in the unmodified message packet and the modifications to the information portion.
Claim 19
Independent Claim
147 words
A method of transmitting a message packet between source and destination nodes via a network having a plurality of routing nodes, each message packet comprising a plurality of sets of information bits constituting an information portion and a set of checking bits, all sets containing the same number of bits in a sequence of bit locations between a bit location of least significance to a bit location of most significance, and each checking bit having been generated by taking the logical sum of bits having the same significance in all of the sets, wherein a method of modifying the message packet is effected at at least one node in the network, this method comprising: modifying the information portion of said message packet; and altering the checking bits by using only the set of checking bits in the unmodified message packet and the modifications to the information portion.
Claim 20
Dependent Claim
127 words
Circuitry for modifying a message packet comprising a plurality of sets of information bits constituting an information portion of said packet and a set of checking bits, all sets containing the same number of bits in a sequence of bit locations between a bit location of least significance to a bit location of most significance, and each checking bit having been generated by taking the logical sum of bits having the same significance in all the sets, said circuitry comprising: an input circuit for receiving said message packet; means for modifying the information portion of said message packet; and a checking bit generator operable to modify the checking bits by using only the checking bits received in the message packet and the modifications to the information portion.
Claim 21
Dependent Claim
127 words
Circuitry for modifying a message packet comprising a plurality of sets of information bits constituting an information portion of said packet and a set of checking bits, all sets containing the same number of bits in a sequence of bit locations between a bit location of least significance to a bit location of most significance, and each checking bit having been generated by taking the logical sum of bits having the same significance in all the sets, said circuitry comprising: an input circuit for receiving said message packet; means for modifying the information portion of said message packet; and a checking bit generator operable to modify the checking bits by using only the checking bits received in the message packet and the modifications to the information portion.
Claim 22
Dependent Claim
34 words
Circuitry according to claim 18 wherein the checking bit generator comprises logic circuitry for taking the exclusive-OR of checking bits with modified information bits having the same place of significance in their respective sets.
Claim 23
Dependent Claim
141 words
A routing switch for receiving and routing message packets comprising a plurality of sets of information bits constituting an information portion of said packet and a set of checking bits, all sets containing the same number of bits in a sequence of bit locations between a bit location of least significance to a bit location of most significance, and each checking bit having been generated by taking the logical sum of bits having the same significance in all the sets, each routing switch comprising circuitry for modifying a message packet, said modifying circuitry comprising: an input circuit for receiving said message packets; means for modifying the information portion of said message packet; and a checking bit generator operable to modify the checking bits by using only the checking bits received in the message packet and the modifications to the information portion.
Claim 24
Dependent Claim
141 words
A routing switch for receiving and routing message packets comprising a plurality of sets of information bits constituting an information portion of said packet and a set of checking bits, all sets containing the same number of bits in a sequence of bit locations between a bit location of least significance to a bit location of most significance, and each checking bit having been generated by taking the logical sum of bits having the same significance in all the sets, each routing switch comprising circuitry for modifying a message packet, said modifying circuitry comprising: an input circuit for receiving said message packets; means for modifying the information portion of said message packet; and a checking bit generator operable to modify the checking bits by using only the checking bits received in the message packet and the modifications to the information portion.
Claim 25
Dependent Claim
28 words
A routing switch according to claim 20 which comprises a header deletion circuit for deleting a set of bits from said information portion before routing the message packet.
Claim 26
Dependent Claim
28 words
A routing switch according to claim 21 which comprises header addition circuitry for adding a set of address bits to said information portion before routing the message packet.
Claim 27
Dependent Claim
28 words
A routing switch according to claim 20 which comprises header addition circuitry for adding a set of address bits to said information portion before routing the message packet.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-09-03 | 2000-03-04 | 2000-09-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-09-03 | 2004-03-04 | 2004-09-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-09-03 | 2008-03-04 | 2008-09-03 | $7700.00 | Window Closed / Lapsed |