US5103451A
Expired / Lapsed
US
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Parallel cyclic redundancy check circuit
Assignee: General Dynamics Mission Systems Inc
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Filing: 1990-01-29
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Granted: 1992-04-07
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Expires: 2010-01-29
Abstract
Abstract A method and circuitry for generating N-bit parallel CRC code from an N-bit parallel data input source. A generating polynomial function is used to express an array of exclusive-OR gates to which the N-bit parallel data inputs are applied. A plurality of N latches is provided and connected to the exclusive-OR gate array in a feedback fashion to provide the plurality of N-bit parallel CRC codes according to the polynomial function.
Inventors
- 👤 Craig R. Fossey
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 17:38
CPC Classifications
H; H03; H03M; H03M13/00; H03M13/03; H03M13/05; H03M13/09; H03M13/091; G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
198 words
A parallel Cyclic Redundancy Check (CRC) generator/checker circuit for providing N-bit parallel CRC code output from an N-bit parallel data input of a digital source, said parallel CRC generator circuit comprising: a plurality of exclusive-OR gating means connected to said digital source and said gating means operating in response to said N-bit parallel data input to produce a plurality of binary outputs according to a predefined generating polynomial function; said plurality of exclusive-OR gating means including; a plurality of first exclusive-OR gating means connected to said digital source via said N-bit parallel data input; a plurality of second exclusive-OR gating means connected to said plurality of first exclusive-OR gating means, to said digital source and to said latching means; a plurality of third exclusive-OR gating means connected to said pluralities of first and second exclusive-OR gating means and to said plurality of latching means; and a plurality of fourth exclusive-OR gating means connected between said plurality of third exclusive-OR gating means and said plurality of latching means; and a plurality of latching means connected to said gating means and said latching operating to store certain ones of said plurality of binary outputs representing said N-bit parallel CRC code.
Claim 2
Dependent Claim
198 words
A parallel Cyclic Redundancy Check (CRC) generator/checker circuit for providing N-bit parallel CRC code output from an N-bit parallel data input of a digital source, said parallel CRC generator circuit comprising: a plurality of exclusive-OR gating means connected to said digital source and said gating means operating in response to said N-bit parallel data input to produce a plurality of binary outputs according to a predefined generating polynomial function; said plurality of exclusive-OR gating means including; a plurality of first exclusive-OR gating means connected to said digital source via said N-bit parallel data input; a plurality of second exclusive-OR gating means connected to said plurality of first exclusive-OR gating means, to said digital source and to said latching means; a plurality of third exclusive-OR gating means connected to said pluralities of first and second exclusive-OR gating means and to said plurality of latching means; and a plurality of fourth exclusive-OR gating means connected between said plurality of third exclusive-OR gating means and said plurality of latching means; and a plurality of latching means connected to said gating means and said latching operating to store certain ones of said plurality of binary outputs representing said N-bit parallel CRC code.
Claim 3
Dependent Claim
22 words
A parallel CRC generator/checker circuit as claimed in claim 1, wherein said plurality of latching means includes a plurality of flip-flop means.
Claim 4
Dependent Claim
30 words
A parallel CRC generator/checker circuit as claimed in claim 2, wherein said plurality of flip-flop means includes N flip-flops, each flip-flop producing 1 bit of said N-bit parallel CRC code.
Claim 5
Dependent Claim
77 words
A parallel CRC generator/checker circuit as claimed in claim 3, wherein there is further included: means for resetting connected to each of said N flip-flops, said means for resetting operating to place each of said N flip-flops in a predetermined initial state; and means for clocking connected to each of said plurality of N flip-flops, said means for clocking causing each of said flip-flops to store a corresponding bit of said N bits of parallel CRC code.
Claim 6
Dependent Claim
51 words
A parallel CRC generator/checker circuit as claimed in claim 1, wherein said plurality of parallel binary outputs are produced according to said predefined generating polynomial function P(X)=P.sub.n X.sup.n +P.sub.n-1 X.sup.n-1 +. . . +P.sub.1 X+P.sub.0 where n=N the number of parallel bits of CRC code; and "+" is an exclusive-OR operation.
Claim 7
Independent Claim
94 words
A method for generating N bits of parallel CRC code output from an N-bit parallel data input, said method including the steps of: expressing a serial linear feedback CRC circuit of N bits according to a predefined generating polynomial function; converting said expressed serial CRC circuit to a parallel circuit of length N-bits; deriving equations for each of said N bits of parallel CRC code from said N bits of parallel data input; and expressing said parallel CRC circuit with an array of exclusive-OR gates and flip-flops according to said predefined generating polynomial function.
Claim 8
Independent Claim
94 words
A method for generating N bits of parallel CRC code output from an N-bit parallel data input, said method including the steps of: expressing a serial linear feedback CRC circuit of N bits according to a predefined generating polynomial function; converting said expressed serial CRC circuit to a parallel circuit of length N-bits; deriving equations for each of said N bits of parallel CRC code from said N bits of parallel data input; and expressing said parallel CRC circuit with an array of exclusive-OR gates and flip-flops according to said predefined generating polynomial function.
Claim 9
Dependent Claim
32 words
A method for generating N-bit parallel CRC code as claimed in claim 6, wherein there is further included the step of selecting a number of bits (N) for said parallel CRC circuit.
Claim 10
Dependent Claim
30 words
A method for generating N-bit parallel CRC code as claimed in claim 7, wherein there is further included the step of minimizing the parallel CRC circuit utilizing Boolean algebra techniques.
Claim 11
Dependent Claim
53 words
A method for generating N-bit parallel CRC code as claimed in claim 10, wherein there is further included the step of using for said predefined generating polynomial function P(X)=P.sub.n X.sup.n +P.sub.n-1 X.sup.n-1 +. . . +P.sub.1 X+P.sub.0 where n=N the number of parallel bits of CRC code; and "+" is an exclusive-OR operation.
Claim 12
Dependent Claim
47 words
A method for generating N-bit parallel CRC code as claimed in claim 6, wherein there is further included the step of determining a preferred generator polynomial function wherein the order of said preferred generator polynomial function=K and N is a product of the prime factors of K.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-04-07 | 1995-10-07 | 1996-04-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-04-07 | 1999-10-07 | 2000-04-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-04-07 | 2003-10-07 | 2004-04-07 | $7700.00 | Window Closed / Lapsed |