Three-dimensional multimodule HDI arrays with heat spreading

Claim 1

A multichip circuit module, comprising: a first semiconductor chip defining length, width and height dimensions, and including metallic contacts on one side thereof, said first semiconductor chip producing heat during operation thereof; a first ceramic substrate defining mutually parallel upper and lower surfaces, and an aperture in said upper surface having length and width dimensions at least equal to said length and width dimensions of said first semiconductor chip, and having a depth dimension substantially equal to said depth dimension of said first semiconductor chip, but less than the separation between said upper and lower surfaces of said first ceramic substrate; first chip holding means for holding said first semiconductor chip in said aperture in said first ceramic substrate, with said side of said first semiconductor chip having said contacts facing away from said aperture, whereby said side of said first semiconductor chip having said contacts is substantially coplanar with said upper surface of said first ceramic substrate, and said heat generated by said first semiconductor chip during operation is conducted, at least in part, to said first ceramic substrate; a first sheet of dielectric film of a material having relatively low thermal conductivity, said first sheet of dielectric film overlying said upper surface of said first ceramic substrate and said side of said first semiconductor chip having said contacts, said first sheet of dielectric film supporting a pattern of electrical conductors, and also including electrically conductive through vias registered with said pattern of electrical conductors and with said contacts of said first semiconductor chip, for coupling electrical energy to said first semiconductor chip during operation; a second semiconductor chip defining length, width and height dimensions, and also including metal contacts on one side thereof; a second ceramic substrate defining mutually parallel upper and lower surfaces, and also defining an aperture having length and width dimensions at least equal to said length and width dimensions of said second semiconductor chip, and having a depth dimension substantially equal to said depth dimension of said second semiconductor chip; second chip holding means for holding said second semiconductor chip in said aperture of said second ceramic substrate, with said side of said second semiconductor chip having said contacts facing away from said aperture of said second ceramic substrate, whereby said side of said second semiconductor chip having said contacts is substantially coplanar with said upper surface of said second ceramic substrate; a second sheet of dielectric film of a material having a relatively low thermal conductivity, said second sheet of dielectric film overlying said upper surface of said second ceramic substrate and said side of said second semiconductor chip having said contacts, said second sheet of dielectric film defining a lower surface adjacent said upper surface of said second ceramic substrate and said side of said second semiconductor chip having said contacts, and an upper surface bearing a pattern of conductors, said second sheet of dielectric film also including a plurality of electrically conductive through vias extending from said upper surface to said lower surface of said second sheet of dielectric film, said through vias being registered with, and in electrical contact with, said contacts of said second semiconductor chip, said second sheet of dielectric film also including a further plurality of through apertures extending from said upper surface to said lower surface of said second sheet of dielectric film at locations remote from said aperture in said second ceramic substrate; mechanical coupling means coupled to said second sheet of dielectric film and to said first ceramic substrate, for mechanically coupling said lower surface of said first ceramic substrate to said upper surface of said second sheet of dielectric film, whereby heat generated by said first semiconductor chip tends to be blocked by said second dielectric sheet, undesirably tending to raise the temperature of said first semiconductor chip by reducing thermal conduction from said first semiconductor chip to said second ceramic substrate; thermally conductive means filling said further plurality of through apertures in said second dielectric sheet, for providing low-thermal-resistance paths for the flow of heat from said first semiconductor chip through said bottom surface of said first ceramic substrate, through said thermally conductive means filling said further plurality of apertures in said second dielectric sheet, to said second ceramic substrate.