Multi-function electronic component, especially negative dynamic resistance element, and corresponding method of fabrication

Claim 2

An electronic component comprising, integrated within the same semiconductor structure: a first semiconductor area forming an insulated-gate field-effect transistor having a drain, a source, and an insulated gate; a second semiconductor area forming a lateral bipolar transistor having an emitter, a base and a collector region; the first and second semiconductor areas having a common semiconductor layer comprising a channel of the insulated-gate field-effect transistor and in which a base current of the bipolar transistor flows when appropriate voltages are applied to the second semiconductor area during use; the channel of the insulated-gate field-effect transistor being a P channel if the lateral bipolar transistor is an NPN transistor and the channel of the insulated-gate field-effect transistor being an N channel if the lateral bipolar transistor is a PNP transistor; wherein the two semiconductor areas together form a structure exhibiting negative dynamic resistance when appropriate voltages are applied to the semiconductor structure during use.

Claim 3

The electronic component of claim 1, further comprising a semiconductor block supporting said insulated gate of the field-effect transistor, wherein the common semiconductor layer extends in an upper part of the semiconductor block under said gate, a portion of the first semiconductor area that is not part of the common semiconductor layer extends on a side of the common layer, and the second semiconductor area partially lies in a lower part of the semiconductor block and is offset laterally with respect to the first semiconductor area.

Claim 4

The electronic component of claim 2, wherein said collector region comprises an intrinsic collector extending into the lower part of the block up to a predetermined distance from said emitter of the bipolar transistor thereby defining a thickness of said base of the bipolar transistor.

Claim 5

The electronic component of claim 3, characterized in that the thickness of the base is submicronic.

Claim 6

The electronic component of claim 3, further defined as comprising a common metallic contact for the base of the bipolar transistor and the drain of the field-effect transistor and separate metallic contacts for the emitter, the collector region of the bipolar transistor, and the source of the field-effect transistor.

Claim 7

The electronic component of claim 1, wherein the semiconductor structure is further defined as comprising: a semiconductor substrate having a first conductivity, an insulating layer situated on a part of a first face of the substrate, and supporting a first projecting semiconductor region that forms the gate of the field-effect transistor and has the first type of conductivity, a first of semiconductor regions, localized within the substrate on either side of a first end area of the projecting region that form, respectively, the source and the drain, the drain and the source having the first type of conductivity, a second pair of semiconductor regions, localized within the substrate on either side of a second area of the projecting region, opposite the first end area that form respectively the emitter and an extrinsic collector of said collector region and has a second type of conductivity that is opposite to the first type of conductivity, a buried semiconductor layer having the second type of conductivity, located on a face of the substrate which is opposite from the first face of the substrate while being in contact with the region of the second pair that forms the extrinsic collector, and away from the other region of the second pair, a first metallization arranged in contact with the region of the first pair of semiconductor regions that forms the drain, a second metallization arranged in contact with the region of the first pair of semiconductor regions that forms the source, and a third metallization arranged in contact with the projecting region.

Claim 8

The electrical component of claim 6, wherein the projecting region and the four regions of the two pairs of semiconductor regions are more doped than the buried layer.

Claim 9

The electric component of claim 6, wherein the four regions of the two pairs of semiconductor regions are further defined as extending from the first face of the substrate to an opposite face.

Claim 10

The electric component of claim 1, wherein a substrate of the semiconductor structure comprises an insulator.

Claim 11

The electronic component of claim 1, comprising at least three metallic contacts on the base, collector region and emitter of said bipolar transistor.

Claim 12

The electronic component of claim 1, comprising at least three metallic contacts on the gate, source and drain of said field-effect transistor.

Claim 13

The electronic component of claim 1, the component being further defined as comprising metallic contacts at least on the drain, base, collector region and emitter.

Claim 14

A method of using the electronic component of claim 11, comprising: providing an additional fourth metallic contact on the collector region; choosing a bias voltage that is positive if the field-effect transistor is a P-channel field-effect transistor and negative if the field-effect transistor is a N-channel field-effect transistor; and applying the bias voltage to the collector region.

Claim 15

A method of using the electronic component of claim 10, comprising: providing an additional fourth metallic contact on the gate; choosing a bias voltage that is negative if the field-effect transistor is a P-channel field-effect transistor and positive if the field-effect transistor is a N-channel field-effect transistor; and applying the bias voltage to the gate.

Claim 16

A method of using the electric component of claim 12, comprising: biasing an emitter-base junction of the bipolar transistor forward; and biasing a collector-base junction in reverse.

Claim 17

The method of claim 15, comprising: providing a metallic contact on the gate of the field-effect transistor; choosing a bias; and applying the chosen bias to the gate.

Claim 18

The method of claim 15, wherein the negative dynamic resistance is obtained from a collector current/voltage relationship.

Claim 19

An electronic component comprising, integrated within the same semiconductor structure: a first semiconductor area including an insulated gate semiconductor region and a channel semiconductor region of an insulated-gate field effect transistor, and a second semiconductor area including an emitter semiconductor region, a collector semiconductor region and a base semiconductor region of a lateral bipolar transistor, said base region having a first zone and a second zone both located under the insulated gate region, said first zone being horizontally located between the emitter region and a first part of the collector region located under the insulated gate region, said second zone being laterally offset with respect to said first zone and vertically located between the insulated gate region and said first part of the collector region, said first and second semiconductor areas having a common semiconductor layer including the channel region and said second zone of the base region, said first and second semiconductor areas together forming a semiconductor structure adapted to have a negative dynamic resistance.

Claim 20

An electronic component comprising, integrated within the same semiconductor structure: a first semiconductor area including an insulated gate semiconductor region and a channel semiconductor region of an insulated-gate field effect transistor, and a second semiconductor area including an emitter semiconductor region, a collector semiconductor region and a base semiconductor region of a lateral bipolar transistor, said base region having a first zone and a second zone both located under the insulated gate region, said first zone being horizontally located between the emitter region and a first part of the collector region located under the insulated gate region, said second zone being laterally offset with respect to said first zone and vertically located between the insulated gate region and said first part of the collector region, said first and second semiconductor areas having a common semiconductor layer including the channel region and said second zone of the base region, said first and second semiconductor areas together forming a semiconductor structure adapted to have a negative dynamic resistance.

Claim 21

An electronic component, comprising a semiconductor structure comprising: a semiconductor substrate having a first type of conductivity, an insulating layer situated on a part of a first face of the substrate, and supporting a first projecting semiconductor region forming a gate region of an insulated-gate field-effect transistor, and having the first type of conductivity, second and third semiconductor regions, localized within the substrate on either side of a first end area of the first projecting region, forming respectively a source region and a drain region of the insulating-gate field-effect transistor and having the first type of conductivity, fourth and fifth semiconductor regions, localized within the substrate on either side of a second end area of the projecting region, opposite the first end area, and having a second type of conductivity that is opposite to the first type of conductivity, a buried semiconductor layer having the second type of conductivity, and lying within the semiconductor substrate, being spaced from the first face of the substrate while being in contact with the fifth region, and being spaced from the fourth region, and a first metallization arranged in contact with the first projecting region and second and third metallizations arranged respectively in contact with the second region and with the third region.

Claim 22

An electronic component, comprising a semiconductor structure comprising: a semiconductor substrate having a first type of conductivity, an insulating layer situated on a part of a first face of the substrate, and supporting a first projecting semiconductor region forming a gate region of an insulated-gate field-effect transistor, and having the first type of conductivity, second and third semiconductor regions, localized within the substrate on either side of a first end area of the first projecting region, forming respectively a source region and a drain region of the insulating-gate field-effect transistor and having the first type of conductivity, fourth and fifth semiconductor regions, localized within the substrate on either side of a second end area of the projecting region, opposite the first end area, and having a second type of conductivity that is opposite to the first type of conductivity, a buried semiconductor layer having the second type of conductivity, and lying within the semiconductor substrate, being spaced from the first face of the substrate while being in contact with the fifth region, and being spaced from the fourth region, and a first metallization arranged in contact with the first projecting region and second and third metallizations arranged respectively in contact with the second region and with the third region.

Claim 23

A method of using the electric component of claim 19, comprising choosing first, second and third bias voltages adapted for using the electric component as a field effect transistor and applying said first, second and third bias voltages to said first, second and third metallizations.

Claim 24

An electronic component comprising a semiconductor structure comprising: a semiconductor substrate having a first type of conductivity, an insulating layer situated on a part of a first face of the substrate, and supporting a first projecting semiconductor region having the first type of conductivity, second and third semiconductor regions, localized within the substrate on either side of a first end area of the first projecting region, and having the first type of conductivity, said third region forming part of a base region of a lateral bipolar transistor, fourth and fifth semiconductor regions, localized within the substrate on either side of a second end of the projecting region, opposite the first end area, having a second type of conductivity that is opposite to the first type of conductivity, and forming respectively an emitter region and an extrinsic collector region for said lateral bipolar transistor, a buried semiconductor layer having the second type of conductivity, and lying within the semiconductor substrate, being spaced from the first face of the substrate while being in contact with the fifth region, and being spaced from the fourth region, a first metallization arranged in contact with the third semiconductor region, and a second and a third metallizations arranged respectively in contact with the fourth and fifth regions.

Claim 25

An electronic component comprising a semiconductor structure comprising: a semiconductor substrate having a first type of conductivity, an insulating layer situated on a part of a first face of the substrate, and supporting a first projecting semiconductor region having the first type of conductivity, second and third semiconductor regions, localized within the substrate on either side of a first end area of the first projecting region, and having the first type of conductivity, said third region forming part of a base region of a lateral bipolar transistor, fourth and fifth semiconductor regions, localized within the substrate on either side of a second end of the projecting region, opposite the first end area, having a second type of conductivity that is opposite to the first type of conductivity, and forming respectively an emitter region and an extrinsic collector region for said lateral bipolar transistor, a buried semiconductor layer having the second type of conductivity, and lying within the semiconductor substrate, being spaced from the first face of the substrate while being in contact with the fifth region, and being spaced from the fourth region, a first metallization arranged in contact with the third semiconductor region, and a second and a third metallizations arranged respectively in contact with the fourth and fifth regions.

Claim 26

The electric component of claim 21, wherein said first projecting region forms a gate region of an insulated gate field effect transistor, and a fourth metallization is arranged in contact with the first projecting region.

Claim 27

A method of using the electric component of claim 21, comprising choosing first, second and third bias voltages adapted for using the electric component as a bipolar transistor and applying said first, second and third bias voltages to said first, second and third metallizations.

Claim 28

A method of using the electric component of claim 22, comprising: choosing first, second and third bias voltages adapted for using the electric component as a bipolar transistor and applying said first, second and third bias voltages to said first, second and third metallizations, choosing a fourth bias voltage that is negative in the case of a P-channel field-effect transistor and positive in the case of a N-channel field-effect transistor; and applying the fourth bias voltage to the fourth metallization.

Claim 29

An electronic component, comprising a semiconductor structure including: a semiconductor substrate having a first type of conductivity, an insulating layer situated on a part of a first face of the substrate, and supporting a first projecting semiconductor region forming a gate region of an insulated-gate field-effect transistor, and having the first type of conductivity, second and third semiconductor regions, localized within the substrate on either side of a first end area of the first projecting region, and having the first type of conductivity, said second region forming a source region and said third region forming a drain region of the insulating-gate field-effect transistor and part of a base region of a lateral bipolar transistor, fourth and fifth semiconductor regions, localized within the substrate on either side of a second end area of the projecting region, opposite the first end area, and having a second type of conductivity that is opposite to the first type of conductivity, said fourth and fifth regions forming respectively an emitter region and an extrinsic collector region of the lateral bipolar transistor, a buried semiconductor layer having the second type of conductivity, and lying within the semiconductor substrate, being spaced from the first face of the substrate while being in contact with the fifth region, and being spaced from the fourth region, a first metallization arranged in contact with the third semiconductor region, second and third metallizations arranged respectively in contact with the first projecting region and with the second region, and fourth and fifth metallizations arranged respectfully in contact with the fourth and fifth regions, a semiconductor substrate having a first conductivity, an insulating layer situated on a part of a first face of the substrate, and supporting a first projecting semiconductor region that forms the gate of the field-effect transistor and has the first type of conductivity, a first pair of semiconductor regions, localized within the substrate on either side of a first end area of the projecting region that form, respectively, the source and the drain, the drain and the source having the first type of conductivity, a second pair of semiconductor regions, localized within the substrate on either side of a second area of the projecting region, opposite the first end area that form respectively the emitter and an extrinsic collector of said collector region and has a second type of conductivity that is opposite to the first type of conductivity, a buried semiconductor layer having the second type of conductivity, located on a face of the substrate which is opposite from the first face of the substrate while being in contact with the region of the second pair that forms the extrinsic collector, and away from the other region of the second pair, a first metallization arranged in contact with the region of the first pair of semiconductor regions that forms the drain, a second metallization arranged in contact with the region of the first pair of semiconductor regions that forms the source, and a third metallization arranged in contact with the projecting region.

Claim 30

An electronic component, comprising a semiconductor structure including: a semiconductor substrate having a first type of conductivity, an insulating layer situated on a part of a first face of the substrate, and supporting a first projecting semiconductor region forming a gate region of an insulated-gate field-effect transistor, and having the first type of conductivity, second and third semiconductor regions, localized within the substrate on either side of a first end area of the first projecting region, and having the first type of conductivity, said second region forming a source region and said third region forming a drain region of the insulating-gate field-effect transistor and part of a base region of a lateral bipolar transistor, fourth and fifth semiconductor regions, localized within the substrate on either side of a second end area of the projecting region, opposite the first end area, and having a second type of conductivity that is opposite to the first type of conductivity, said fourth and fifth regions forming respectively an emitter region and an extrinsic collector region of the lateral bipolar transistor, a buried semiconductor layer having the second type of conductivity, and lying within the semiconductor substrate, being spaced from the first face of the substrate while being in contact with the fifth region, and being spaced from the fourth region, a first metallization arranged in contact with the third semiconductor region, second and third metallizations arranged respectively in contact with the first projecting region and with the second region, and fourth and fifth metallizations arranged respectfully in contact with the fourth and fifth regions, a semiconductor substrate having a first conductivity, an insulating layer situated on a part of a first face of the substrate, and supporting a first projecting semiconductor region that forms the gate of the field-effect transistor and has the first type of conductivity, a first pair of semiconductor regions, localized within the substrate on either side of a first end area of the projecting region that form, respectively, the source and the drain, the drain and the source having the first type of conductivity, a second pair of semiconductor regions, localized within the substrate on either side of a second area of the projecting region, opposite the first end area that form respectively the emitter and an extrinsic collector of said collector region and has a second type of conductivity that is opposite to the first type of conductivity, a buried semiconductor layer having the second type of conductivity, located on a face of the substrate which is opposite from the first face of the substrate while being in contact with the region of the second pair that forms the extrinsic collector, and away from the other region of the second pair, a first metallization arranged in contact with the region of the first pair of semiconductor regions that forms the drain, a second metallization arranged in contact with the region of the first pair of semiconductor regions that forms the source, and a third metallization arranged in contact with the projecting region.