US5172209A
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Integral Bi-CMOS logic circuit
Assignee: Samsung Electronics Co Ltd
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Filing: 1991-05-10
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Granted: 1992-12-15
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Expires: 2011-05-10
Abstract
Abstract An integral Bi-CMOS logic circuit includes a pair of first transistors and a pair of second transistors. The pair of the first transistors includes a P-type MOS transistor receiving an input signal through its gate, and an NPN-type bipolar transistor with its base connected to the drain of the P-type MOS transistor outputting a first output signal. The pair of the second transistors includes an N-type MOS transistor receiving the input signal through its gate, and a PNP bipolar transistor with its base connected to the drain of the N-type MOS transistor outputting the first output signal. A final output signal is outputted through a common emitter of the bipolar transistors.
Inventors
- 👤 Deugsoo Chang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 06:44
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/40; H10D84/401; H10D84/403; H10D84/406; H10D84/01; H10D84/0107; H10D84/0109
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
106 words
An integral Bi-CMOS logic circuit comprising: a pair of first transistors including a first MOS transistor for receiving an input signal through its gate, and a first bipolar transistor with its base connected to the drain of the first MOS transistor for outputting a first output signal; and a pair of second transistors including a second MOS transistor for receiving the input signal through its gate, and a second bipolar transistor with its base connected to the drain of the second MOS transistor for outputting the first output signal, the first and second bipolar transistors having a common emitter terminal for outputting a final output signal.
Claim 2
Dependent Claim
106 words
An integral Bi-CMOS logic circuit comprising: a pair of first transistors including a first MOS transistor for receiving an input signal through its gate, and a first bipolar transistor with its base connected to the drain of the first MOS transistor for outputting a first output signal; and a pair of second transistors including a second MOS transistor for receiving the input signal through its gate, and a second bipolar transistor with its base connected to the drain of the second MOS transistor for outputting the first output signal, the first and second bipolar transistors having a common emitter terminal for outputting a final output signal.
Claim 3
Dependent Claim
21 words
The circuit of claim 1, wherein the first MOS transistor is a P-type, and the first bipolar transistor is an NPN-type.
Claim 4
Dependent Claim
21 words
The circuit of claim 1, wherein the second MOS transistor is an N-type, and the second bipolar transistor is a PNP-type.
Claim 5
Dependent Claim
34 words
The circuit of claim 1, wherein pair of the first transistors are formed on an n- well of a P-type substrate, and the pair of second transistors are formed directly on the P-type substrate.
Claim 6
Dependent Claim
53 words
The circuit of claim 1, wherein the pair of the first transistors are formed on an n- epitaxial layer which is in turn formed on an n+ buried layer, and the pair of the second transistors are formed on a P- epitaxial layer which is in turn formed on a P+ buried layer.
Claim 7
Dependent Claim
83 words
The circuit of claim 2, wherein the drain region of the P-type first MOS transistor is formed as a P- and P+ dual diffusion structure within an n- well, a source region of the P-type first MOS transistor is also formed within the n- well, a collector region of the NPN-type first bipolar transistor is formed as the n- well, and an n+ emitter region of the NPN-type first bipolar transistor is formed within a P- region of the NPN-type first bipolar transistor.
Claim 8
Dependent Claim
26 words
The circuit of claim 6, wherein the drain region of the P-type first MOS transistor serves as a base region of the NPN-type first bipolar transistor.
Claim 9
Dependent Claim
61 words
The circuit of claim 3, wherein the second N-type MOS transistor has a drain region comprising an n- and n+ dual diffusion structure within a P-type substrate, an n+ source region is also formed on the P-type substrate, the PNP-type second bipolar transistor has a collector region formed on the P-substrate, and an n+ emitter region formed within the n- region.
Claim 10
Dependent Claim
25 words
The circuit of claim 8, wherein the drain region of the N-type second MOS transistor serves as base region of the PNP-type second bipolar transistor.
Claim 11
Dependent Claim
26 words
The circuit of claim 1, wherein the pair of first transistors are formed in a completely complementary type with respect to the second pair of transistors.
Claim 12
Dependent Claim
80 words
The circuit of claim 4, wherein a drain region of the first MOS transistor is P-type and is formed as a P- and P+ dual diffusion structure within the n- well, a source region of the first MOS transistor is also formed within the n- well, a collector region of the first bipolar transistor is formed as the n- well, and an n+ emitter region of the first bipolar transistor is formed within a P-region of the first bipolar transistor.
Claim 13
Dependent Claim
26 words
The circuit of claim 11, wherein the drain region of the P-type first MOS transistor serves as a base region of the NPN-type first bipolar transistor.
Claim 14
Dependent Claim
71 words
The circuit of claim 4, wherein the second MOS transistor is N-type and has a drain region comprising an n- and n+ dual diffusion structure within the P-type substrate, an n+ source region is also formed on the substrate, and the second bipolar transistor is PNP-type and has a collector region formed on the P-substrate, and a p+ emitter region is formed within an n- region of the second bipolar transistor.
Claim 15
Dependent Claim
26 words
The circuit of claim 13, wherein the drain region of the N-type second MOS transistor serves as a base region of the PNP-type second bipolar transistor.
Claim 16
Dependent Claim
21 words
The circuit of claim 10, wherein the first MOS transistor is a P-type, and the first bipolar transistor is an NPN-type.
Claim 17
Dependent Claim
21 words
The circuit of claim 10, wherein the second MOS transistor is an N-type, and the second bipolar transistor is a PNP-type.
References Cited (Backward Citations)
No citation records indexed.
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| 3.5 Years (Year 4) | 1995-12-15 | 1996-06-15 | 1996-12-15 | $2000.00 | Window Closed / Lapsed |
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