Patent US4719169A successfully refreshed from Google Patents.
US4891533A
Expired / Lapsed
US
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MOS-cascoded bipolar current sources in non-epitaxial structure
Assignee: Analog Devices Inc
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Filing: 1984-02-17
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Granted: 1990-01-02
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Expires: 2004-02-17
Abstract
Abstract A 16-bit D/A converter formed on a single monolithic chip and having two cascaded stages each including a 256-R resistor string DAC. The analog output voltage of the first stage is coupled to the second stage by two buffer amplifiers each formed by a non-epitaxial process using a P-type substrate. The amplifiers include NMOS and PMOS-cascoded bipolar current sources arranged to avoid the use of metallization to provide for electrical interconnections within the source.
Inventors
- 👤 Peter R. Holloway
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 10:14
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/40; H10D84/401; H10D84/403; H10D84/409; H03; H03M; H03M1/00; H03M1/66; H03M1/68; H03M1/682; H10D84/406; H03M1/74; H03M1/76; H03M1/765
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
122 words
In a monolithic integrated circuit having a P-type substrate with an N-well therein; a P-type MOS-cascoded bipolar current source connected in said circuit and comprising: first and second separate P-type diffusions in said N-well to serve as the drain and source of a PMOS device; a gate positioned between said first and second P-type diffusions; a third P-type diffusion in said N-well separate from said first and second diffusions and serving as the emitter of a lateral PNP transistor having said second P-type diffusion as its collector and said N-well as its base;and electrodes making connection with said first and third P-type diffusions and said N-well; whereby said PMOS source and said bipolar collector are electrically connected without requiring a diffusion-to-metal-to-diffusion interconnection.
Claim 2
Dependent Claim
122 words
In a monolithic integrated circuit having a P-type substrate with an N-well therein; a P-type MOS-cascoded bipolar current source connected in said circuit and comprising: first and second separate P-type diffusions in said N-well to serve as the drain and source of a PMOS device; a gate positioned between said first and second P-type diffusions; a third P-type diffusion in said N-well separate from said first and second diffusions and serving as the emitter of a lateral PNP transistor having said second P-type diffusion as its collector and said N-well as its base;and electrodes making connection with said first and third P-type diffusions and said N-well; whereby said PMOS source and said bipolar collector are electrically connected without requiring a diffusion-to-metal-to-diffusion interconnection.
Claim 3
Dependent Claim
34 words
An integrated circuit is claimed in claim 1, including an N-type diffusion in said N-well to make connection between an electrode and said N-well, said N-well providing the back-gate connection for said PMOS device.
Claim 4
Dependent Claim
18 words
An integrated circuit as claimed in claim 2, wherein said second P-type diffusion surrounds said third P-type diffusion.
Claim 5
Dependent Claim
19 words
An integrated circuit as claimed in claim 3, wherein said N-type diffusion extends partially around said second P-type diffusion.
Claim 6
Dependent Claim
48 words
An integrated circuit as claimed in claim 4, wherein said second P-type diffusion is a ring at least approximately square in shape; said N-type diffusion being at least approximately U-shaped, with the two arms of the "U" extending along two respective parallel sides of the square P-type diffusion.
Claim 7
Dependent Claim
182 words
In a monolithic integrated circuit having a P-type substrate with an N-well therein; an N-type MOS-cascoded bipolar current source connected in said circuit and comprising: a P-type diffusion in said N-well to serve as the base of an NPN transistor; an N-type diffusion in said P-type diffusion to serve as the emitter of said NPN transistor; electrodes contacting said P-type and N-type diffusions to make connection to said base and said emitter; said N-well serving as the collector for said NPN transistor; an N-type diffusion in said P-type substrate, externally of said N-well, to serve as the drain of an NMOS device; an electrode contacting said external N-type diffusion; a gate for said NMOS device adjacent said external N-type diffusion; said N-well comprising N-type material extending to a region which is adjacent said gate but on the side thereof which is opposite said external N-type diffusion, said N-type material serving as the source of said NMOS device and as the collector of said NPN transistor; whereby said NPN collector and said NMOS source are effectively connected electrically without requiring a diffusion-to-metal-to-diffusion interconnection.
Claim 8
Dependent Claim
182 words
In a monolithic integrated circuit having a P-type substrate with an N-well therein; an N-type MOS-cascoded bipolar current source connected in said circuit and comprising: a P-type diffusion in said N-well to serve as the base of an NPN transistor; an N-type diffusion in said P-type diffusion to serve as the emitter of said NPN transistor; electrodes contacting said P-type and N-type diffusions to make connection to said base and said emitter; said N-well serving as the collector for said NPN transistor; an N-type diffusion in said P-type substrate, externally of said N-well, to serve as the drain of an NMOS device; an electrode contacting said external N-type diffusion; a gate for said NMOS device adjacent said external N-type diffusion; said N-well comprising N-type material extending to a region which is adjacent said gate but on the side thereof which is opposite said external N-type diffusion, said N-type material serving as the source of said NMOS device and as the collector of said NPN transistor; whereby said NPN collector and said NMOS source are effectively connected electrically without requiring a diffusion-to-metal-to-diffusion interconnection.
Claim 9
Dependent Claim
38 words
An integrated circuit as claimed in claim 6, wherein said N-well includes an initial N-type diffusion, said N-type material comprising an N+ diffusion partially overlapping said initial N-type diffusion and extending to the side edge of said gate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-01-01 | 1993-07-03 | 1994-01-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-01-01 | 1997-07-03 | 1998-01-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-01-01 | 2001-07-03 | 2002-01-02 | $7700.00 | Window Closed / Lapsed |