US4864372A
Expired / Lapsed
US
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Field effect transistor
Assignee: Northrop Grumman Guidance and Electronics Co Inc
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Filing: 1986-03-03
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Granted: 1989-09-05
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Expires: 2006-03-03
Abstract
Abstract This disclosure depicts a novel semiconductor device and the method of making it. A novel field effect transistor (FET) has a channel region which is heavily doped under the gate and between the gate and the source of the FET. The channel region between the gate and the drain is lightly doped. The FET is formed on a heavily doped semiconductor substrate. The method of making the novel FET comprises providing a mask layer over a lightly doped channel region and forming openings in the mask layer such that a portion of the mask is located at the gate location and has a predetermined width and height.
Inventors
- 👤 Sanehiko Kakihana
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 05:43
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/061; H10D30/0612; H10D30/0614; H10D62/00; H10D62/10; H10D62/17; H10D62/213; H10D62/221; H10P; H10P30/00; H10P30/20; H10P30/22; H10P30/221; H10P30/222
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
111 words
A field effect transistor comprising: a. a semi-insulating substrate of semiconductor; b. a heavily doped drain region of semiconductor spaced a predetermined distance from a heavily doped source region of semiconductor on said substrate; c. a heavily doped channel region of semiconductor extending a predetermined distance from said source region to a gate location located intermediate said source and drain regions, said heavily doped channel region also extending under said gate location and in direction contact with a gate terminal at said gate location; and d. a lightly doped channel region of semiconductor located between said gate location and said drain region and extending also under said heavily doped channel region.
Claim 2
Dependent Claim
111 words
A field effect transistor comprising: a. a semi-insulating substrate of semiconductor; b. a heavily doped drain region of semiconductor spaced a predetermined distance from a heavily doped source region of semiconductor on said substrate; c. a heavily doped channel region of semiconductor extending a predetermined distance from said source region to a gate location located intermediate said source and drain regions, said heavily doped channel region also extending under said gate location and in direction contact with a gate terminal at said gate location; and d. a lightly doped channel region of semiconductor located between said gate location and said drain region and extending also under said heavily doped channel region.
Claim 3
Dependent Claim
13 words
The field effect transistor of claim 1 wherein said semiconductor comprises gallium arsenide.
Claim 4
Dependent Claim
33 words
The field effect transistor of claim 1 wherein said heavily doped channel region has a thickness of approximately 0.6 micron and said lightly doped channel region has a thickness of approximately one micron.
Claim 5
Dependent Claim
37 words
The field effect transistor of claim 1 wherein said lightly doped channel region has a predetermined thickness and said heavily doped channel region has a predetermined thickness less than said thickness of said lightly doped channel region.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-09-04 | 1993-03-06 | 1993-09-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-09-04 | 1997-03-06 | 1997-09-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-09-04 | 2001-03-06 | 2001-09-05 | $7700.00 | Window Closed / Lapsed |