Circuit and method for providing a known logic state at insufficient supply voltage

Claim 2

A logic circuit having an output line that assumes a known state when a supply voltage rises above a predetermined level, said logic circuit including an MOS logic transistor connected between a supply voltage source and the output line and connected to receive an input signal on a gate thereof, said MOS logic transistor having a first voltage threshold, comprising: an MOS state controlling transistor having a threshold voltage less than the first voltage threshold, said MOS state controlling transistor and said MOS logic transistor being of opposite conductivity type; said MOS state controlling transistor being connected between the output line and a reference potential source, and having its gate connected to the gate of said MOS logic transistor; a resistor connected between the supply voltage and the gate of said MOS state controlling transistor; whereby if said supply voltage rises above the voltage threshold of said MOS state controlling transistor, said MOS state controlling transistor conducts to produce a reference potential on the output line.

Claim 3

The circuit of claim 1 wherein said MOS state controlling transistor is an NMOS transistor and said MOS logic transistor is a PMOS transistor.

Claim 4

A circuit to force a logic circuit to a known state when a supply voltage rises above a predetermined level, said logic circuit including a pair of MOS logic transistors of opposite conductivity type connected in series between a supply voltage source and a reference potential source, one of said MOS logic transistors is connected between the supply voltage source and an output line, comprising: at least one MOS state controlling transistor having a threshold voltage less than a threshold voltage of one of said MOS logic transistors, said at least one MOS state controlling transistor and said one of said MOS logic transistors being of the same conductivity type; said MOS state controlling transistor being connected in parallel with said one of said MOS logic transistors, and having a control element connected to an input voltage source to which a control element of said one of said MOS logic transistors is connected; whereby if said supply voltage rises above the threshold of said MOS state controlling transistor, said MOS state controlling transistor conducts to produce said known logic state at the output line.

Claim 5

A circuit to force a logic circuit to a known state when a supply voltage rises above a predetermined level, said logic circuit including a pair of MOS logic transistors of opposite conductivity type connected in series between a supply voltage source and a reference potential source, one of said MOS logic transistors is connected between the supply voltage source and an output line, comprising: at least one MOS state controlling transistor having a threshold voltage less than a threshold voltage of one of said MOS logic transistors, said at least one MOS state controlling transistor and said one of said MOS logic transistors being of the same conductivity type; said MOS state controlling transistor being connected in parallel with said one of said MOS logic transistors, and having a control element connected to an input voltage source to which a control element of said one of said MOS logic transistors is connected; whereby if said supply voltage rises above the threshold of said MOS state controlling transistor, said MOS state controlling transistor conducts to produce said known logic state at the output line.

Claim 6

The circuit of claim 3 wherein said MOS state controlling transistor and said one of said MOS logic transistors are PMOS transistors.

Claim 7

The circuit of claim 3 wherein said MOS state controlling transistor and said one of said MOS logic transistors are NMOS transistors.

Claim 8

The circuit of claim 4 further comprising a resistor connected between said control element of said MOS state controlling transistor and said reference potential source.

Claim 9

The circuit of claim 5 further comprising a resistor connected between said control element of said MOS state controlling transistor and said supply voltage source.

Claim 10

A circuit to force a logic circuit to a known state when a supply voltage rises above a predetermined level, said logic circuit including a pair of MOS logic transistors of opposite conductivity type connected in series between a supply voltage source and a reference potential source, one of said MOS logic transistors is connected between the supply voltage source and an output line, comprising: a pair of MOS state controlling transistors each having a threshold voltage less than a threshold voltage of one of said MOS logic transistors, said MOS state controlling transistors and said one of said MOS logic transistors being of the same conductivity type; said pair of MOS state controlling transistors being connected in series, the series being connected in parallel with said one of said MOS logic transistors, and each having a control element connected to an input voltage source to which a control element of said one of said MOS logic transistors is connected; whereby if said supply voltage rises above the threshold voltage of said MOS state controlling transistors, said pair of MOS state controlling transistors conducts to produce said known logic state at the output line.

Claim 11

A circuit to force a logic circuit to a known state when a supply voltage rises above a predetermined level, said logic circuit including a pair of MOS logic transistors of opposite conductivity type connected in series between a supply voltage source and a reference potential source, one of said MOS logic transistors is connected between the supply voltage source and an output line, comprising: a pair of MOS state controlling transistors each having a threshold voltage less than a threshold voltage of one of said MOS logic transistors, said MOS state controlling transistors and said one of said MOS logic transistors being of the same conductivity type; said pair of MOS state controlling transistors being connected in series, the series being connected in parallel with said one of said MOS logic transistors, and each having a control element connected to an input voltage source to which a control element of said one of said MOS logic transistors is connected; whereby if said supply voltage rises above the threshold voltage of said MOS state controlling transistors, said pair of MOS state controlling transistors conducts to produce said known logic state at the output line.

Claim 12

The circuit of claim 8 wherein said pair of MOS state controlling transistors and said one of said MOS logic transistors are PMOS transistors.

Claim 13

The circuit of claim 8 wherein said pair of MOS state controlling transistors and said one of said MOS logic transistors are NMOS transistors.

Claim 14

The circuit of claim 9 further comprising a resistor connected between said control elements of said pair of MOS state controlling transistors and said reference potential source.

Claim 15

The circuit of claim 10 further comprising a resistor connected between said control elements of said pair of MOS state controlling transistors and said supply voltage source.

Claim 16

A NOR logic circuit, comprising: a first pair of MOS logic transistors of the same conductivity type connected in series between a supply voltage source and an output line, each of said MOS logic transistors having a control element connected to a respective logic signal input line; a second pair of MOS logic transistors of the same conductivity type connected in parallel between the output line and a reference potential source, said first and second pairs of MOS logic transistors being of opposite conductivity type, each of said second pair of MOS logic transistors having a control element connected to a respective logic signal input line; and an MOS state controlling transistor having a threshold voltage less than a threshold voltage of one of said MOS logic transistors of said second pair of MOS logic transistors, said MOS state controlling transistor and said one of said second pair of MOS logic transistors being of the same conductivity type; said MOS state controlling transistor being connected in parallel with said one of said MOS logic transistors of said second pair of MOS logic transistors, and having a control element connected to one of said logic signal input lines; whereby if said supply voltage rises above the threshold voltage of said MOS state controlling transistor, said MOS state controlling transistor conducts to produce said known logic state on said output line.

Claim 17

A NOR logic circuit, comprising: a first pair of MOS logic transistors of the same conductivity type connected in series between a supply voltage source and an output line, each of said MOS logic transistors having a control element connected to a respective logic signal input line; a second pair of MOS logic transistors of the same conductivity type connected in parallel between the output line and a reference potential source, said first and second pairs of MOS logic transistors being of opposite conductivity type, each of said second pair of MOS logic transistors having a control element connected to a respective logic signal input line; and an MOS state controlling transistor having a threshold voltage less than a threshold voltage of one of said MOS logic transistors of said second pair of MOS logic transistors, said MOS state controlling transistor and said one of said second pair of MOS logic transistors being of the same conductivity type; said MOS state controlling transistor being connected in parallel with said one of said MOS logic transistors of said second pair of MOS logic transistors, and having a control element connected to one of said logic signal input lines; whereby if said supply voltage rises above the threshold voltage of said MOS state controlling transistor, said MOS state controlling transistor conducts to produce said known logic state on said output line.

Claim 18

The circuit of claim 13 wherein said MOS state controlling transistor and said one of said MOS logic transistors of said second pair of MOS logic transistors are NMOS transistors.

Claim 19

The circuit of claim 14 further comprising a resistor connected between said control element of said MOS state controlling transistor and said supply voltage source.

Claim 20

A NAND logic circuit, comprising: a first pair of MOS logic transistors of the same conductivity type connected in series between a reference potential source and an output line, each of said MOS logic transistors having a control element connected to a respective logic signal input line; a second pair of MOS logic transistors of the same conductivity type connected in parallel between the output line and a supply voltage source, said first and second pairs of MOS logic transistors being of opposite conductivity type, each of said second pair of MOS logic transistors having a control element connected to a respective logic signal input line; and an MOS state controlling transistor having a threshold voltage less than a threshold voltage of one of said MOS logic transistors of said second pair of MOS logic transistors, said MOS state controlling transistor and said one of said second pair of MOS logic transistors being of the same conductivity type; said MOS state controlling transistor being connected in parallel with said one of said MOS logic transistors of said second pair of MOS logic transistors, and having a control element connected to one of said logic signal input lines; whereby if said supply voltage rises above the voltage threshold of said MOS state controlling transistor, said MOS state controlling transistor conducts to produce said known logic state on said output line.

Claim 21

A NAND logic circuit, comprising: a first pair of MOS logic transistors of the same conductivity type connected in series between a reference potential source and an output line, each of said MOS logic transistors having a control element connected to a respective logic signal input line; a second pair of MOS logic transistors of the same conductivity type connected in parallel between the output line and a supply voltage source, said first and second pairs of MOS logic transistors being of opposite conductivity type, each of said second pair of MOS logic transistors having a control element connected to a respective logic signal input line; and an MOS state controlling transistor having a threshold voltage less than a threshold voltage of one of said MOS logic transistors of said second pair of MOS logic transistors, said MOS state controlling transistor and said one of said second pair of MOS logic transistors being of the same conductivity type; said MOS state controlling transistor being connected in parallel with said one of said MOS logic transistors of said second pair of MOS logic transistors, and having a control element connected to one of said logic signal input lines; whereby if said supply voltage rises above the voltage threshold of said MOS state controlling transistor, said MOS state controlling transistor conducts to produce said known logic state on said output line.

Claim 22

The circuit of claim 16 wherein said MOS state controlling transistor and said one of said MOS logic transistors of said second pair of MOS logic transistors are PMOS transistors.

Claim 23

The circuit of claim 12 further comprising a resistor connected between said control element of said MOS state controlling transistor and said reference potential source.

Claim 26

The circuit of claim 19 wherein said output control transistor is an NMOS transistor and said logic transistor is a PMOS transistor.