US5438280A
Expired / Lapsed
US
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Input circuit receiving input signal of TTL level
Assignee: Renesas Electronics Corp
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Filing: 1993-11-30
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Granted: 1995-08-01
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Expires: 2013-11-30
Abstract
Abstract A signal input circuit having a CMOS inverter for receiving an input signal of a TTL level is disclosed. This circuit includes a first transistor of one channel type connected between a first power terminal and an output terminal and having a gate connected to an input terminal, a second transistor of an opposite channel type connected between a second power terminal and the output terminal and having a gate connected to the input terminal, and a current gain control circuit coupled to the first transistor for controlling the current gain of the first transistor to a first value when a power voltage is at a first level and to a second value when the power voltage is at a second level.
Inventors
- 👤 Mitsutoshi Sugawara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 12:08
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/088; H03K19/0021; H03K19/0027; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018521
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
132 words
An input circuit comprising a first transistor of one channel type connected between a first power terminal and an output terminal and having a gate connected to an input terminal, a second transistor of an opposite channel type connected between a second power terminal and said output terminal and having a gate connected to said input terminal, a third and a fourth transistor of said one channel type connected in series between said first power terminal and said output terminal, said third transistor having a gate connected to said input terminal, and means coupled to a gate of said fourth transistor for turning said fourth transistor ON when a power voltage between said first and second power terminals takes a first level and OFF when said power voltage takes a second level.
Claim 2
Dependent Claim
132 words
An input circuit comprising a first transistor of one channel type connected between a first power terminal and an output terminal and having a gate connected to an input terminal, a second transistor of an opposite channel type connected between a second power terminal and said output terminal and having a gate connected to said input terminal, a third and a fourth transistor of said one channel type connected in series between said first power terminal and said output terminal, said third transistor having a gate connected to said input terminal, and means coupled to a gate of said fourth transistor for turning said fourth transistor ON when a power voltage between said first and second power terminals takes a first level and OFF when said power voltage takes a second level.
Claim 3
Dependent Claim
37 words
The circuit as claimed in claim 1, wherein said one channel type is a P-channel type and said opposite channel type is an N-channel type, said first level being smaller in absolute value than said second level.
Claim 4
Dependent Claim
37 words
The circuit as claimed in claim 1, wherein said one channel type is an N-channel type and Said opposite channel type is a P-channel type, said first level being larger in absolute value than said second level.
Claim 5
Dependent Claim
145 words
An input circuit comprising a first transistor one channel type connected between a first power terminal and an output terminal and having a gate connected to an input terminal, a second transistor of an opposite channel type connected between a second power terminal and said output terminal and having a gate connected to said input terminal, a third transistor of said one channel type inserted in series to said first transistor between said first power terminal and said output terminal and having a gate connected to said input terminal, a fourth transistor of said one channel type connected in parallel to said third transistor, and means coupled to a gate of said fourth transistor for turning said fourth transistor ON when a power voltage between said first and second power terminals takes a first level and OFF when said power voltage takes a second level.
Claim 6
Dependent Claim
145 words
An input circuit comprising a first transistor one channel type connected between a first power terminal and an output terminal and having a gate connected to an input terminal, a second transistor of an opposite channel type connected between a second power terminal and said output terminal and having a gate connected to said input terminal, a third transistor of said one channel type inserted in series to said first transistor between said first power terminal and said output terminal and having a gate connected to said input terminal, a fourth transistor of said one channel type connected in parallel to said third transistor, and means coupled to a gate of said fourth transistor for turning said fourth transistor ON when a power voltage between said first and second power terminals takes a first level and OFF when said power voltage takes a second level.
Claim 7
Dependent Claim
37 words
The circuit as claimed in claim 4, wherein said one channel type is a P-channel type and said opposite channel type is an N-channel type, said first level being smaller in absolute value than said second level.
Claim 8
Dependent Claim
37 words
The circuit as claimed in claim 4, wherein said one channel type is an N-channel type and said opposite channel type is a P-channel type, said first level being larger in absolute value than said second level.
Claim 9
Dependent Claim
116 words
An input circuit comprising a first transistor of one channel type connected between a first power terminal and an output terminal and having a gate connected to an input terminal, a second transistor of an opposite channel type connected between a second power terminal and said output terminal and having a gate connected to said input terminal, a third and a fourth transistors of said one channel type connected in series between said first power terminal and said output terminal, said third transistor being rendered conductive when a power voltage between said first and second power terminals takes a first level and nonconductive when said power voltage takes a second level different from said first level.
Claim 10
Dependent Claim
116 words
An input circuit comprising a first transistor of one channel type connected between a first power terminal and an output terminal and having a gate connected to an input terminal, a second transistor of an opposite channel type connected between a second power terminal and said output terminal and having a gate connected to said input terminal, a third and a fourth transistors of said one channel type connected in series between said first power terminal and said output terminal, said third transistor being rendered conductive when a power voltage between said first and second power terminals takes a first level and nonconductive when said power voltage takes a second level different from said first level.
Claim 11
Dependent Claim
133 words
An input circuit comprising a first transistor of one channel type connected between a first power terminal and an output terminal and having a gate connected to an input terminal, a second transistor of an opposite channel type connected between a second power terminal and said output terminal and having a gate connected to said input terminal, a third transistor of said one channel type connected in series to said first transistor between said first power terminal and said output terminal, and a fourth transistor of said one channel type connected in parallel to said third transistor, said fourth transistor being rendered nonconductive when a power voltage between said first and second power terminals takes a first level and conductive when said power voltage takes a second level different from said first level.
Claim 12
Dependent Claim
133 words
An input circuit comprising a first transistor of one channel type connected between a first power terminal and an output terminal and having a gate connected to an input terminal, a second transistor of an opposite channel type connected between a second power terminal and said output terminal and having a gate connected to said input terminal, a third transistor of said one channel type connected in series to said first transistor between said first power terminal and said output terminal, and a fourth transistor of said one channel type connected in parallel to said third transistor, said fourth transistor being rendered nonconductive when a power voltage between said first and second power terminals takes a first level and conductive when said power voltage takes a second level different from said first level.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-07-31 | 1999-01-30 | 1999-08-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-07-31 | 2003-01-30 | 2003-08-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-07-31 | 2007-01-30 | 2007-08-01 | $7700.00 | Window Closed / Lapsed |