One-chip semiconductor integrated circuit device having a digital signal processing circuit and an analog signal processing circuit

Claim 2

A one-chip semiconductor integrated circuit device comprising: digital signal processing means for processing a digital signal in synchronism with a first clock signal; and analog signal processing means for sampling an analog input signal in synchronism with a second clock signal having a phase different from that of said first clock signal, said analog signal processing means comprising an analog-to-digital converter having a sample and hold circuit, and a latch circuit, said sample and hold circuit operating in synchronism with said second clock signal, and said latch circuit latching an output signal of said sample and hold circuit in synchronism with a third clock signal having a phase different from the phases of the first and second clock signals.

Claim 3

A one-chip semiconductor integrated circuit device as claimed in claim 1, further comprising delay means for delaying said first clock signal by a predetermined delay time and for outputting said second clock signal which rises and falls at timings different from timings at which said first clock signal rises and falls.

Claim 4

A one-chip semiconductor integrated circuit device as claimed in claim 1, further comprising clock generating means for generating said first clock signal.

Claim 5

A one-chip semiconductor integrated circuit device as claimed in claim 2, wherein: said one-chip semiconductor integrated circuit device has a power supply line coupled to at least said digital signal processing means and said analog input signal processing means; a power supply voltage of said power supply line has a noise component which is temporarily generated when said first clock signal rises and falls; and said predetermined delay time is selected so that said second clock signal has a duration time during which said second clock signal is less affected by said noise component.

Claim 6

A one-chip semiconductor integrated circuit device as claimed in claim 2, wherein: said one-chip semiconductor integrated circuit device has a power supply line coupled to at least said digital signal processing means and said analog input signal processing means; a power supply voltage of said power supply line has a noise component which is temporarily generated when said first clock signal rises and falls; and said predetermined delay time is selected so that said second clock signal rises and falls after said noise component becomes substantially zero.

Claim 7

A one-chip semiconductor integrated circuit device as claimed in claim 1, wherein: said analog signal processing means comprises converting means for converting said analog input signal to a corresponding digital signal and a digital-to-analog converter having a sample and hold circuit; and said sample and hold circuit samples and holds said corresponding digital signal in synchronism with said second clock signal and outputs an output signal.

Claim 8

A one-chip semiconductor integrated circuit device as claimed in claim 2, wherein said delay means comprises a plurality of inverters connected in series, and capacitors which are connected between said inverters and ground.

Claim 9

A one-chip semiconductor integrated circuit device as claimed in claim 1, wherein said one-chip semiconductor integrated circuit device is a one-chip microcomputer.

Claim 10

A one-chip semiconductor integrated circuit device as claimed in claim 1, wherein said second and third clock signals have respective timings so as to rise or fall when no noise component is superimposed on a power supply voltage of said power supply line.

Claim 11

A one-chip semiconductor integrated circuit device as claimed in claim 1, further comprising: first delay means for delaying said first clock signal by a first predetermined delay time and for deriving said second clock signal from a delayed first clock signal; and second delay means for delaying a latch signal by a second predetermined delay time and for deriving said third clock signal from a delayed latch signal.

Claim 12

A one-chip semiconductor integrated circuit device as claimed in claim 10, wherein said first and second predetermined delay times are enough long to make it possible for said second and third clock signals to rise or fall when no noise component is superimposed on a power supply voltage of said power supply line.

Claim 13

A one-chip semiconductor integrated circuit device comprising: digital signal processing means for processing a digital signal in synchronism with a first clock signal; timing generating means for generating a second clock signal from said first clock signal, said second clock signal having a cycle different from that of said first clock signal and rising and falling when said first clock signal rises and falls; delay means coupled to said timing generating means, for delaying said second clock signal by a predetermined delay time and for outputting a third clock signal which rises and falls at timings different from timings at which said first clock signal rises and falls; and analog signal processing means, directly coupled to said delay means, for sampling an analog input signal in synchronism with said third clock signal, said analog signal processing means comprising an analog-to-digital converter having a sample and hold circuit, and a latch circuit, said sample and hold circuit operating in synchronism with said third clock signal, and said latch circuit latching an output signal of said sample and hold circuit in synchronism with a fourth clock signal having a phase different from the phases of the first and third clock signals.

Claim 14

A one-chip semiconductor integrated circuit device comprising: digital signal processing means for processing a digital signal in synchronism with a first clock signal; timing generating means for generating a second clock signal from said first clock signal, said second clock signal having a cycle different from that of said first clock signal and rising and falling when said first clock signal rises and falls; delay means coupled to said timing generating means, for delaying said second clock signal by a predetermined delay time and for outputting a third clock signal which rises and falls at timings different from timings at which said first clock signal rises and falls; and analog signal processing means, directly coupled to said delay means, for sampling an analog input signal in synchronism with said third clock signal, said analog signal processing means comprising an analog-to-digital converter having a sample and hold circuit, and a latch circuit, said sample and hold circuit operating in synchronism with said third clock signal, and said latch circuit latching an output signal of said sample and hold circuit in synchronism with a fourth clock signal having a phase different from the phases of the first and third clock signals.

Claim 15

A one-chip semiconductor integrated circuit chip as claimed in claim 12, further comprising clock generating means for generating said first clock signal.

Claim 16

A one-chip semiconductor integrated circuit device as claimed in claim 12, wherein: said one-chip semiconductor integrated circuit device has a power supply line coupled to at least said digital signal processing means and said analog signal processing means; a power supply voltage of said power supply line has a noise component which is temporarily generated when said first clock signal rises and falls; and said predetermined delay time is selected so that said third clock signal has a duration time during which said third clock signal is less affected by said noise component.

Claim 17

A one-chip semiconductor integrated circuit device as claimed in claim 12, wherein: said one-chip semiconductor integrated circuit device has a power supply line coupled to at least said digital signal processing means and said analog signal processing means; a power supply voltage of said power supply line has a noise component which is temporarily generated when said first clock signal rises and falls; and said predetermined delay time is selected so that said third clock signal rises and falls after said noise component becomes substantially zero.

Claim 18

A one-chip semiconductor integrated circuit device as claimed in claim 12, wherein: said analog signal processing means comprises converting means for converting said analog input signal to a corresponding digital signal and a digital-to-analog converter having a sample and hold circuit; and said sample and hold circuit samples and holds said corresponding digital signal in synchronism with said third clock signal and outputs an output signal.

Claim 19

A one-chip semiconductor integrated circuit device as claimed in claim 12, wherein said delay means comprises inverters connected in series, and capacitors which are connected between said inverters and ground.

Claim 20

A one-chip semiconductor integrated circuit device as claimed in claim 12, wherein said one-chip semiconductor integrated circuit device is a one-chip microcomputer.

Claim 21

A one-chip semiconductor integrated circuit device as claimed in claim 12, wherein said third and fourth clock signals have respective timings so as to rise or fall when no noise component is superimposed on a power supply voltage of said power supply line.

Claim 22

A one-chip semiconductor integrated circuit device as claimed in claim 12, further comprising: first delay means for delaying said second clock signal by a first predetermined delay time and for deriving said third clock signal from a delayed second clock signal; and second delay means for delaying a latch signal by a second predetermined delay time and for deriving said fourth clock signal from a delayed latch signal.

Claim 23

A one-chip semiconductor integrated circuit device as claimed in claim 20, wherein said first and second predetermined delay times are enough long to make it possible for said third and fourth clock signals to rise or fall when no noise component is superimposed on a power supply voltage of said power supply line.

Claim 24

A one-chip semiconductor integrated circuit device comprising: digital signal processing means for processing a digital signal in synchronism with a first clock signal; timing generating means for generating a second clock signal and a third clock signal from said first clock signal, each of said second and third clock signals having a cycle different from that of said first clock signal and rising and falling when said first clock signal rises and falls; delay means, coupled to said timing generating means, for delaying said second and third clock signals by respective predetermined delay times and for outputting fourth and fifth clock signals which rise and fall at timings different from timings at which said first clock signal rises and falls; and analog signal processing means, directly coupled to said delay means, for performing a predetermined analog operation on an analog input signal in synchronism with said fourth and fifth clock signals, wherein: said analog signal processing means comprises an analog-to-digital converter having a sample and hold circuit and a latch circuit; said sample and hold circuit samples and holds said analog input signal in synchronism with said fourth clock signal and output an output signal; and said latch circuit latches said output signal in synchronism with said fifth clock signal.

Claim 25

A one-chip semiconductor integrated circuit device comprising: digital signal processing means for processing a digital signal in synchronism with a first clock signal; timing generating means for generating a second clock signal and a third clock signal from said first clock signal, each of said second and third clock signals having a cycle different from that of said first clock signal and rising and falling when said first clock signal rises and falls; delay means, coupled to said timing generating means, for delaying said second and third clock signals by respective predetermined delay times and for outputting fourth and fifth clock signals which rise and fall at timings different from timings at which said first clock signal rises and falls; and analog signal processing means, directly coupled to said delay means, for performing a predetermined analog operation on an analog input signal in synchronism with said fourth and fifth clock signals, wherein: said analog signal processing means comprises an analog-to-digital converter having a sample and hold circuit and a latch circuit; said sample and hold circuit samples and holds said analog input signal in synchronism with said fourth clock signal and output an output signal; and said latch circuit latches said output signal in synchronism with said fifth clock signal.

Claim 26

A one-chip semiconductor integrated circuit device as claimed in claim 22, further comprising clock generating means for generating said first clock signal.

Claim 27

A one-chip semiconductor integrated circuit device as claimed in claim 22, wherein: said one-chip semiconductor integrated circuit device has a power supply line coupled to at least said digital signal processing means and said analog input signal processing means; a power supply voltage of said power supply line has a noise component which is temporarily generated when said first clock signal rises and falls; and each of said respective predetermined delay times is selected so that each of said fourth and fifth clock signals has a duration time during which said fourth and fifth clock signals are less affected by said noise component.

Claim 28

A one-chip semiconductor integrated circuit device as claimed in claim 22, wherein: said one-chip semiconductor integrated circuit device has a power supply line coupled to at least said digital signal processing means and said analog signal processing means; a power supply voltage of said power supply line has a noise component which is temporarily generated when said first clock signal rises and falls; and each of said respective predetermined delay times is selected so that each of said fourth and fifth clock signals rises and falls after said noise component becomes substantially zero.

Claim 29

A one-chip semiconductor integrated circuit device as claimed in claim 25, wherein each of said first and second delay means comprises inverters connected in series, and capacitors coupled between said inverters and ground.

Claim 30

A one-chip semiconductor integrated circuit device as claimed in claim 22, wherein: said delay means comprises first delay means for delaying said second clock signal by a first predetermined delay time and for outputting said fourth clock signal, and second delay means for delaying said third clock signal by a second predetermined delay time and for outputting said fifth clock signal.

Claim 31

A one-chip semiconductor integrated circuit device as claimed in claim 27, wherein said first predetermined delay time is substantially identical to said second predetermined delay time.

Claim 32

A one-chip semiconductor integrated circuit deice as claimed in claim 27, wherein said first predetermined delay time is different from said second predetermined delay time.

Claim 33

A one-chip semiconductor integrated circuit device as claimed in claim 22, wherein said one-chip semiconductor integrated circuit device is a one-chip microcomputer.