Low-voltage high-performance dual-feedback dynamic sense amplifier

Claim 2

A sense amplifier circuit for generating first and second complementary latched data outputs indicative of a voltage difference between a first and a second data input, comprising: a first transistor having a source, a drain, and a gate connected to said first data input, a second transistor having a source, a drain, and a gate connected to said second data input, output generating means connected to said sources of said first and said second transistor for generating a first and a second data output indicative of said first and second data input, first switching means, responsive to said first data output of said output generating means being provided to a control terminal of said first switching means, for providing a first reference voltage to said drain of said first transistor, second switching means, responsive to said second data output of said output generating means being provided to a control terminal of said second switching means, for providing said first reference voltage to said drain of said second transistor, third switching means for providing, in response to a first control signal being provided to a control terminal of said third switching means while said first and second switching means are activated, said first reference voltage to said output generating means such that said first data output of said output generating means is latched to a first voltage level determined by said first reference voltage and said second data output of said output generating means is latched to a second voltage level complementary to said first voltage level thereby generating said first and second complementary latched data outputs indicative of said voltage difference between said first and second data inputs, and equalizing means connected to said first and second data outputs of said output generating means for equalizing voltages respectively on said first and second data outputs in response to a second control signal being provided to at least one terminal of said equalizing means.

Claim 3

The sense amplifier circuit as recited in claim 1, wherein said first switching means comprises: a third transistor having a source connected to said first reference voltage, a drain connected to said drain of said first transistor, and a gate connected to said first data output of said output generating means, said gate being said control terminal of said first switching means.

Claim 4

The sense amplifier circuit as recited in claim 1, wherein said second switching means comprises: a fourth transistor having a source connected to said first reference voltage, a drain connected to said drain of said second transistor, and a gate connected to said second data output of said output generating means, said gate being said control terminal of said second switching means.

Claim 5

The sense amplifier circuit as recited in claim 1, wherein said third switching means comprises: a fifth transistor having a source connected to said first reference voltage, a drain connected to said output generating means, and a gate connected to said first control signal, said gate being said control terminal of said third switching means.

Claim 6

The sense amplifier circuit as recited in claim 1, wherein said output generating means comprises: a first inverter having said first data output of said output generating means as a data output, a data input, and a reference voltage input connected to said third switching means for receiving said first reference voltage from said second switching means, and a second inverter having said second data output of said output generating means as a data output, a data input, and a reference voltage input connected to said reference voltage input of said first inverter and said third switching means for receiving said first reference voltage from said second switching means, wherein said data output of said second inverter is connected to said source of said second transistor and to said data input of said first inverter, said data output of said first inverter is connected to said source of said first transistor and to said data input of said second inverter, and said data output of said first inverter and said data output of said second inverter are provided as activating signals to said second and first switching means respectively.

Claim 7

The sense amplifier circuit as recited in claim 5, further comprising: a first capacitor connected between said gate of said first transistor and said data output of said second inverter, to provide charge compensation for said first transistor, and a second capacitor connected between said gate of said second transistor and said data output of said first inverter, to provide charge compensation for said second transistor.

Claim 8

The sense amplifier circuit as recited in claim 5, wherein said first inverter comprises: a sixth transistor having a source, a drain, and a gate, and a seventh transistor having a source, a drain, and a gate, wherein said source of said sixth transistor acts as said reference voltage input of said first inverter, said gates of said sixth and seventh transistors are connected together to form said data input of said first inverter, and said drains of said sixth and seventh transistors are connected together to form said data output of said first inverter.

Claim 9

The sense amplifier circuit as recited in claim 5, wherein said second inverter comprises: a eighth transistor having a source, a drain, and a gate, and a ninth transistor having a source, a drain, and a gate, wherein said source of said eighth transistor acts as said reference voltage input of said second inverter, said gates of said eighth and ninth transistors are connected together to form said data input of said second inverter, and said drains of said eighth and ninth transistors are connected together to form said data output of said second inverter.

Claim 10

The sense amplifier circuit as recited in claim 1, wherein said equalizing means comprises: a tenth transistor having a source, a drain, and a gate connected to said second control signal, and an eleventh transistor having a source, a drain, and a gate connected to an inverted version of said second control signal, wherein said source of said tenth transistor is connected to said drain of said eleventh transistor and to said first data output, and said drain of said tenth transistor is connected to said source of said eleventh transistor and to said second data output.

Claim 13

A computer system comprising: a microprocessor, a data bus connected to said microprocessor, and a sense amplifier circuit connected to said data bus, wherein said sense amplifier circuit generates a first and second complementary latched data outputs indicative of a voltage difference between a first and a second data line, and said sense amplifier circuit includes: a first transistor having a source, a drain, and a gate connected to said first data input, a second transistor having a source, a drain, and a gate connected to said second data input, output generating means connected to said sources of said first and second transistors for generating a first and a second data output indicative of said first and second data input, first switching means, responsive to said first data output of said output generating means being provided to a control terminal of said first switching means, for providing a first reference voltage to said drain of said first transistor, second switching means, responsive to said second data output of said output generating means being provided to a control terminal of said second switching means, for providing said first reference voltage to said drain of said second transistor, third switching means for providing, in response to a first control signal being provided to a control terminal of said third switching means while said first and second switching means are activated, said first reference voltage to said output generating means such that said first data output of said output generating means is latched to a first voltage level determined by said first reference voltage and said second data output of said output generating means is latched to a second voltage level complementary to said first voltage level thereby generating said first and second complementary latched data outputs indicative of said voltage difference between said first and second data inputs, and equalizing means connected to said first and second data outputs of said output generating means for equalizing voltages respectively on said first and second data outputs in response to a second control signal being provided to at least one terminal of said equalizing means.

Claim 14

A computer system comprising: a microprocessor, a data bus connected to said microprocessor, and a sense amplifier circuit connected to said data bus, wherein said sense amplifier circuit generates a first and second complementary latched data outputs indicative of a voltage difference between a first and a second data line, and said sense amplifier circuit includes: a first transistor having a source, a drain, and a gate connected to said first data input, a second transistor having a source, a drain, and a gate connected to said second data input, output generating means connected to said sources of said first and second transistors for generating a first and a second data output indicative of said first and second data input, first switching means, responsive to said first data output of said output generating means being provided to a control terminal of said first switching means, for providing a first reference voltage to said drain of said first transistor, second switching means, responsive to said second data output of said output generating means being provided to a control terminal of said second switching means, for providing said first reference voltage to said drain of said second transistor, third switching means for providing, in response to a first control signal being provided to a control terminal of said third switching means while said first and second switching means are activated, said first reference voltage to said output generating means such that said first data output of said output generating means is latched to a first voltage level determined by said first reference voltage and said second data output of said output generating means is latched to a second voltage level complementary to said first voltage level thereby generating said first and second complementary latched data outputs indicative of said voltage difference between said first and second data inputs, and equalizing means connected to said first and second data outputs of said output generating means for equalizing voltages respectively on said first and second data outputs in response to a second control signal being provided to at least one terminal of said equalizing means.

Claim 15

The sense amplifier circuit as recited in claim 11, wherein said first switching means comprises: a third transistor having a source connected to said first reference voltage, a drain connected to said drain of said first transistor, and a gate connected to said first data output of said output generating means, said gate being said control terminal of said first switching means.

Claim 16

The sense amplifier circuit as recited in claim 11, wherein said second switching means comprises: a fourth transistor having a source connected to said first reference voltage, a drain connected to said drain of said second transistor, and a gate connected to said second data output of said output generating means, said gate being said control terminal of said second switching means.

Claim 17

The sense amplifier circuit as recited in claim 11, wherein said third switching means comprises: a fifth transistor having a source connected to said first reference voltage, a drain connected to said output generating means, and a gate connected to said first control signal, said gate being said control terminal of said third switching means.

Claim 18

The computer system as recited in claim 11, wherein said output generating means comprises: a first inverter having said first data output of said output generating means as a data output, a data input, and a reference voltage input connected to said third switching means for receiving said first reference voltage from said second switching means, and a second inverter having said second data output of said output generating means as a data output, a data input, and a reference voltage input connected to said reference voltage input of said first inverter and said third switching means for receiving said first reference voltage from said second switching means, wherein said data output of said second inverter is connected to said source of said second transistor and to said data input of said first inverter, said data output of said first inverter is connected to said source of said first transistor and to said data input of said second inverter, and said data output of said first inverter and said data output of said second inverter are provided as activating signals to said second and first switching means respectively.

Claim 19

The computer system as recited in claim 15, further comprising: a first capacitor connected between said gate of said first transistor and said data output of said second inverter, to provide charge compensation for said first transistor, and a second capacitor connected between said gate of said second transistor and said data output of said first inverter, to provide charge compensation for said second transistor.

Claim 20

The computer system as recited in claim 15, wherein said first inverter comprises: a sixth transistor having a source, a drain, and a gate, and a seventh transistor having a source, a drain, and a gate, wherein said source of said sixth transistor acts as said reference voltage input of said first inverter, said gates of said sixth and seventh transistors are connected together to form said data input of said first inverter, and said drains of said sixth and seventh transistors are connected together to form said data output of said first inverter.

Claim 21

The computer system as recited in claim 15, wherein said second inverter comprises: a eighth transistor having a source, a drain, and a gate, and a ninth transistor having a source, a drain, and a gate, wherein said source of said eighth transistor acts as said reference voltage input of said second inverter, said gates of said eighth and ninth transistors are connected together to form said data input of said second inverter, and said drains of said eighth and ninth transistors are connected together to form said data output of said second inverter.

Claim 22

The computer system as recited in claim 11, wherein said equalizing means comprises: a tenth transistor having a source, a drain, and a gate connected to said second control signal, and an eleventh transistor having a source, a drain, and a gate connected to an inverted version of said second control signal, wherein said source of said tenth transistor is connected to said drain of said eleventh transistor and to said first data output, and said drain of said tenth transistor is connected to said source of said eleventh transistor and to said second data output.