Patent US5543335A successfully refreshed from Google Patents.
US5543335A
Expired / Lapsed
US
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Advanced power device process for low drop
Assignee: IXYS LLC
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Filing: 1993-05-05
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Granted: 1996-08-06
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Expires: 2013-05-05
Abstract
Abstract A method for fabricating a power semiconductor device with a low forward voltage drop using polymer passivation. A polymer passivation layer is deposited over the device. Impurities are introduced into the backside of the device by ion implantation, the backside of the device being on the opposite side of the semiconductor device from the polymer passivation layer. The impurities are then diffused into the semiconductor device.
Inventors
- 👤 Nathan Zommer
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 03:59
CPC Classifications
H; H10; H10P; H10P95/00; Y; Y10; Y10S; Y10S438/00; Y10S438/958
Claims Analysis
Total Claims: 43
Claim 1
Independent Claim
69 words
A method for fabricating a semiconductor device, the method comprising the steps of: depositing a polymer passivation layer over a semiconductor wafer; subsequent to the step of depositing a polymer passivation layer, introducing impurities into a backside of the semiconductor wafer, the backside of the semiconductor wafer being on the opposite side of the semiconductor wafer from the polymer passivation layer; and diffusing the impurities into the semiconductor wafer.
Claim 2
Independent Claim
69 words
A method for fabricating a semiconductor device, the method comprising the steps of: depositing a polymer passivation layer over a semiconductor wafer; subsequent to the step of depositing a polymer passivation layer, introducing impurities into a backside of the semiconductor wafer, the backside of the semiconductor wafer being on the opposite side of the semiconductor wafer from the polymer passivation layer; and diffusing the impurities into the semiconductor wafer.
Claim 3
Dependent Claim
12 words
The method of claim 1 wherein the polymer passivation layer comprises polyimide.
Claim 4
Dependent Claim
16 words
The method of claim 1 wherein the step of introducing impurities is accomplished by ion implantation.
Claim 5
Dependent Claim
14 words
The method of claim 1 further comprising the step of performing an activation anneal.
Claim 6
Dependent Claim
19 words
The method of claim 4 wherein the activation anneal occurs between the temperatures of 350° C. and 450° C.
Claim 7
Dependent Claim
19 words
The method of claim 4 wherein the activation anneal occurs between the temperatures of 400° C. and 420° C.
Claim 8
Dependent Claim
19 words
The method of claim 1 wherein the impurities are n-type dopants for a semiconductor wafer having an n-type substrate.
Claim 9
Dependent Claim
19 words
The method of claim 1 wherein the impurities are p-type dopants for a semiconductor wafer having an n-type substrate.
Claim 10
Dependent Claim
45 words
The method of claim 1, further comprising the steps of: depositing dielectric material on the semiconductor wafer; curing the polymer passivation layer; forming apertures in the dielectric material and the polymer passivation layer; and depositing a metal layer on the backside of the semiconductor wafer.
Claim 11
Dependent Claim
12 words
The method of claim 9 wherein the dielectric material comprises silicon nitride.
Claim 12
Dependent Claim
12 words
The method of claim 9 wherein the polymer passivation layer comprises polyimide.
Claim 13
Dependent Claim
16 words
The method of claim 9 wherein the step of introducing impurities is accomplished by ion implantation.
Claim 14
Dependent Claim
14 words
The method of claim 9 further comprising the step of performing an activation anneal.
Claim 15
Dependent Claim
19 words
The method of claim 13 wherein the activation anneal occurs between the temperatures of 350° C. and 450° C.
Claim 16
Dependent Claim
19 words
The method of claim 13 wherein the activation anneal occurs between the temperatures of 400° C. and 420° C.
Claim 17
Dependent Claim
19 words
The method of claim 9 wherein the impurities are n-type dopants for a semiconductor wafer having an n-type substrate.
Claim 18
Dependent Claim
19 words
The method of claim 9 wherein the impurities are p-type dopants for a semiconductor wafer having an n-type substrate.
Claim 19
Dependent Claim
19 words
The method of claim 9 wherein the impurities are p-type dopants for a semiconductor wafer having a p-type substrate.
Claim 20
Dependent Claim
19 words
The method of claim 9 wherein the impurities are n-type dopants for a semiconductor wafer having a p-type substrate.
Claim 21
Dependent Claim
19 words
The method of claim 1 wherein the impurities are p-type dopants for a semiconductor wafer having a p-type substrate.
Claim 22
Dependent Claim
19 words
The method of claim 1 wherein the impurities are n-type dopants for a semiconductor wafer having a p-type substrate.
Claim 23
Independent Claim
103 words
A method for fabricating a semiconductor device, the method comprising the steps of: depositing dielectric material on a semiconductor wafer; depositing a polymer passivation layer over the dielectric material; curing the polymer passivation layer; forming apertures in the dielectric material and the polymer passivation layer; subsequent to the step of depositing a polymer passivation layer, introducing impurities into a backside of the semiconductor wafer, the backside of the semiconductor wafer being on the opposite side of the semiconductor wafer from the polymer passivation layer; diffusing the impurities into the semiconductor wafer; and depositing a metal layer on the backside of the semiconductor wafer.
Claim 24
Independent Claim
103 words
A method for fabricating a semiconductor device, the method comprising the steps of: depositing dielectric material on a semiconductor wafer; depositing a polymer passivation layer over the dielectric material; curing the polymer passivation layer; forming apertures in the dielectric material and the polymer passivation layer; subsequent to the step of depositing a polymer passivation layer, introducing impurities into a backside of the semiconductor wafer, the backside of the semiconductor wafer being on the opposite side of the semiconductor wafer from the polymer passivation layer; diffusing the impurities into the semiconductor wafer; and depositing a metal layer on the backside of the semiconductor wafer.
Claim 25
Dependent Claim
12 words
The method of claim 22 wherein the dielectric material comprises silicon nitride.
Claim 26
Dependent Claim
12 words
The method of claim 22 wherein the polymer passivation layer comprises polyimide.
Claim 27
Dependent Claim
16 words
The method of claim 22 wherein the step of introducing impurities is accomplished by ion implantation.
Claim 28
Dependent Claim
18 words
The method of claim 22 wherein the step of diffusing is accomplished by means of an activation anneal.
Claim 29
Dependent Claim
19 words
The method of claim 26 wherein the activation anneal occurs between the temperatures of 350° C. and 450° C.
Claim 30
Dependent Claim
19 words
The method of claim 26 wherein the activation anneal occurs between the temperatures of 400° C. and 420° C.
Claim 31
Dependent Claim
19 words
The method of claim 22 wherein the impurities are n-type dopants for a semiconductor wafer having an n-type substrate.
Claim 32
Dependent Claim
19 words
The method of claim 22 wherein the impurities are p-type dopants for a semiconductor wafer having an n-type substrate.
Claim 33
Dependent Claim
19 words
The method of claim 22 wherein the impurities are p-type dopants for a semiconductor wafer having a p-type substrate.
Claim 34
Dependent Claim
19 words
The method of claim 22 wherein the impurities are n-type dopants for a semiconductor wafer having a p-type substrate.
Claim 35
Independent Claim
160 words
A method for fabricating a semiconductor device wherein the forward voltage drop of the semiconductor device is reduced, the method comprising the steps of: depositing silicon nitride on a semiconductor wafer; depositing dielectric material on the silicon nitride; depositing a polyimide passivation layer over the dielectric material; curing the polyimide passivation layer; depositing a photoresist pattern on the polyimide passivation layer; etching apertures in the polyimide passivation layer, the dielectric material, and the silicon nitride; reducing the thickness of the semiconductor wafer with a wafer-thinning operation; subsequent to the step of depositing a polyimide passivation layer ion implanting impurities into a backside of the semiconductor wafer, the backside of the semiconductor wafer being on the opposite side of the semiconductor wafer from the dielectric material and the polyimide passivation layer; diffusing the impurities into the semiconductor wafer; depositing a metal layer on the backside of the semiconductor wafer; and sintering the metal layer and the backside of the semiconductor wafer.
Claim 36
Independent Claim
160 words
A method for fabricating a semiconductor device wherein the forward voltage drop of the semiconductor device is reduced, the method comprising the steps of: depositing silicon nitride on a semiconductor wafer; depositing dielectric material on the silicon nitride; depositing a polyimide passivation layer over the dielectric material; curing the polyimide passivation layer; depositing a photoresist pattern on the polyimide passivation layer; etching apertures in the polyimide passivation layer, the dielectric material, and the silicon nitride; reducing the thickness of the semiconductor wafer with a wafer-thinning operation; subsequent to the step of depositing a polyimide passivation layer ion implanting impurities into a backside of the semiconductor wafer, the backside of the semiconductor wafer being on the opposite side of the semiconductor wafer from the dielectric material and the polyimide passivation layer; diffusing the impurities into the semiconductor wafer; depositing a metal layer on the backside of the semiconductor wafer; and sintering the metal layer and the backside of the semiconductor wafer.
Claim 37
Dependent Claim
14 words
The method of claim 33 further comprising the step of performing an activation anneal.
Claim 38
Dependent Claim
19 words
The method of claim 34 wherein the activation anneal occurs between the temperatures of 350° C. and 450° C.
Claim 39
Dependent Claim
19 words
The method of claim 34 wherein the activation anneal occurs between the temperatures of 400° C. and 420° C.
Claim 40
Dependent Claim
19 words
The method of claim 33 wherein the impurities are n-type dopants for a semiconductor wafer having an n-type substrate.
Claim 41
Dependent Claim
19 words
The method of claim 33 wherein the impurities are p-type dopants for a semiconductor wafer having an n-type substrate.
Claim 42
Dependent Claim
19 words
The method of claim 33 wherein the impurities are p-type dopants for a semiconductor wafer having a p-type substrate.
Claim 43
Dependent Claim
19 words
The method of claim 33 wherein the impurities are n-type dopants for a semiconductor wafer having a p-type substrate.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-08-06 | 2000-02-05 | 2000-08-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-08-06 | 2004-02-05 | 2004-08-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-08-06 | 2008-02-05 | 2008-08-06 | $7700.00 | Window Closed / Lapsed |