US4588472A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of fabricating a semiconductor device
Assignee: Hitachi Ltd
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Filing: 1984-01-26
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Granted: 1986-05-13
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Expires: 2004-01-26
Abstract
Abstract This invention relates to the method of forming a semiconductor device having a diaphragm. A highly doped semiconductor region is formed in the peripheral portion of the semiconductor substrate around the part in which the diaphragm is to be formed, and then that part is etched. Thereby, the diaphragm of a semiconductor pressure sensor can be formed very accurately to a desired shape.
Inventors
- 👤 Isao Shimizu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 17:02
CPC Classifications
H; H10; H10D; H10D48/00; H10D48/50; G; G01; G01L; G01L9/00; G01L9/0041; G01L9/0042; H10P; H10P50/00; H10P50/60; H10P50/64; H10P50/642; H10P50/644; Y; Y10; Y10S; Y10S438/00; Y10S438/914; Y10S438/924; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49082; Y10T29/49103
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
171 words
A method of fabricating a piezoresistive semiconductor pressure sensor having a predetermined diaphragm configuration, comprising the steps of: forming a highly doped region, in a single crystal semiconductor substrate with first and second principal planes facing each other, by covering at least part of said first principal plane by a mask for defining said predetermined diaphragm configuration, said mask having substantially the same configuration as said predetermined diaphragm configuration, and selectively introducing impurities into the portion thereof which is not covered by said mask; forming an epitaxial semiconductor region on said second principal plane; forming semiconductor regions for gauge resistors by selectively introducing impurities into the principal plane of the epitaxial semiconductor region positioned on a portion in which said highly doped region is not formed; and etching a portion of said first principal plane in which said highly doped region is not formed, to thereby form said predetermined diaphragm configuration, whereby a controlled recess providing the predetermined diaphragm configuration, independent of the crystal orientation of the semiconductor substrate, is formed.
Claim 2
Independent Claim
171 words
A method of fabricating a piezoresistive semiconductor pressure sensor having a predetermined diaphragm configuration, comprising the steps of: forming a highly doped region, in a single crystal semiconductor substrate with first and second principal planes facing each other, by covering at least part of said first principal plane by a mask for defining said predetermined diaphragm configuration, said mask having substantially the same configuration as said predetermined diaphragm configuration, and selectively introducing impurities into the portion thereof which is not covered by said mask; forming an epitaxial semiconductor region on said second principal plane; forming semiconductor regions for gauge resistors by selectively introducing impurities into the principal plane of the epitaxial semiconductor region positioned on a portion in which said highly doped region is not formed; and etching a portion of said first principal plane in which said highly doped region is not formed, to thereby form said predetermined diaphragm configuration, whereby a controlled recess providing the predetermined diaphragm configuration, independent of the crystal orientation of the semiconductor substrate, is formed.
Claim 3
Dependent Claim
49 words
The method of fabricating piezoresistive semiconductor pressure sensor as set forth in claim 1, wherein said single crystal semiconductor substrate is a single crystal silicon substrate of which the first and second principal planes are positioned in or adjacent to the (100) plane of said single crystal silicon substrate.
Claim 4
Dependent Claim
26 words
The method of fabricating piezoresistive semiconductor pressure sensor as set forth in claim 2, wherein the etching step is achieved by anisotropic etching using alkaline etchants.
Claim 5
Dependent Claim
38 words
The method of fabricating a piezoresistive semiconductor pressure sensor as set forth in claim 3, wherein said highly doped region has an ion impurity concentration sufficient to prevent etching of said highly doped region by said alkaline etchants.
Claim 6
Dependent Claim
33 words
The method of fabricating a piezoresistive semiconductor pressure sensor as set forth in claim 1, wherein the highly doped region has an ion impurity concentration of at least 10 19 atoms/cm 3 .
Claim 7
Dependent Claim
22 words
The method of fabricating a piezoresistive semiconductor pressure sensor as set forth in claim 1, wherein said predetermined diaphragm configuration is circular.
Claim 8
Dependent Claim
22 words
The method of fabricating a piezoresistive semiconductor pressure sensor as set forth in claim 1, wherein said etching is a chemical etching.
Claim 9
Dependent Claim
49 words
The method of fabricating a piezoresistive semiconductor pressure sensor as set forth in claim 1, further comprising the step of forming another highly doped region by selectively introducing impurities into the second principal plane at a position on the portion in which the highly doped region is not formed.
Claim 10
Dependent Claim
34 words
The method of fabricating a piezoresistive semiconductor pressure sensor as set forth in claim 1, further comprising the step of forming another highly doped region in the second principal plane of the semiconductor substrate.
Claim 11
Dependent Claim
42 words
The method of fabricating a piezoresistive semiconductor pressure sensor as set forth in claim 9, wherein the highly doped region and the another highly doped region are formed at corresponding positions in the first and second principal planes opposed to each other.
Claim 12
Dependent Claim
21 words
The method of fabricatng a piezoresistive semiconductor pressure sensor as set forth in claim 5, wherein said impurities are boron ions.
Claim 13
Dependent Claim
40 words
The method of fabricating a piezoresistive semiconductor pressure sensor as set forth in claim 1, wherein said highly doped region is formed by selectively introducing the impurities and driving the impurities into the substrate to form deep highly doped regions.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-05-12 | 1989-11-11 | 1990-05-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-05-12 | 1993-11-11 | 1994-05-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-05-12 | 1997-11-11 | 1998-05-13 | $7700.00 | Window Closed / Lapsed |