EP0037876A2
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EP
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Electrochemical eroding process for semiconductors
Assignee: International Business Machines Corp
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Filing: 1981-02-05
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Granted: —
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Expires: 2001-02-05
Abstract
Abstract Semiconductor devices (3) are fabricated that have precise uniform thickness regions formed by a self-limiting process in which light (5) generated hole-electron pairs are used as a source of current in electrochemical erosion. A self-aligned MESFET semiconductor structure (Figs. 1 and 4) has the gate (15) positioned in etched undercuts (13, 14) of the source and drain regions (9-12). Arrays of enhancement and depletion mode FET devices can be made on the same substrate.
Inventors
- 👤 Terry Ivan Chappell
- 👤 George David Pettit
- 👤 Jerry Mcpherson Woodall
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 00:44
CPC Classifications
C; C25; C25F; C25F3/00; C25F3/02; C25F3/12; H; H10; H10D; H10D30/00; H10D30/80; H10D30/87; H10D30/877; H10P; H10P50/00; H10P50/60; H10P50/61; H10P50/613; H10P50/617
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
67 words
A process of uniformly electrochemically eroding a semiconductor to a specific dimension by providing in an electrolytic solution (2) a semiconductor (3) having a particular impurity density and thickness illuminating said semiconductor with light (5) of a selected frequency capable of penetrating said semiconductor to a specific depth, and employing photogenerated carrier current flowing into said electrolytic solution to electrochemically erode said semiconductor to said specific depth.
Claim 2
Dependent Claim
67 words
A process of uniformly electrochemically eroding a semiconductor to a specific dimension by providing in an electrolytic solution (2) a semiconductor (3) having a particular impurity density and thickness illuminating said semiconductor with light (5) of a selected frequency capable of penetrating said semiconductor to a specific depth, and employing photogenerated carrier current flowing into said electrolytic solution to electrochemically erode said semiconductor to said specific depth.
Claim 3
Dependent Claim
56 words
The process of Claim 1, wherein said electrochemical erosion self-limits at said specific depth as a result of said semiconductor (3) becoming sufficiently thin that at least hole-electron pair generation is reduced and/or light induced minority carriers are swept into an underlying region and/or majority carrier current conduction out of the electrochemical eroding region is impeded.
Claim 4
Dependent Claim
61 words
A process of electrochemically eroding a region (3b) of a semiconductor member (3) to a precise dimension characterized by applying light (5) to said semiconductor member whereby photogenerated carriers are produced therein and maintaining said semiconductor member in the presence of said light in contact with an electrolytic etching solution (2) until said semiconductor member electrochemically erodes to said precise dimension.
Claim 5
Dependent Claim
61 words
A process of electrochemically eroding a region (3b) of a semiconductor member (3) to a precise dimension characterized by applying light (5) to said semiconductor member whereby photogenerated carriers are produced therein and maintaining said semiconductor member in the presence of said light in contact with an electrolytic etching solution (2) until said semiconductor member electrochemically erodes to said precise dimension.
Claim 6
Dependent Claim
14 words
The process of anyone of the preceding Claims, wherein said semiconductor (3) is GaAs.
Claim 7
Dependent Claim
22 words
The process of Claim 4 wherein said semiconductor region (3b) is epitaxial with a semi-insulating substrate (3a) of GaAs doped with Cr.
Claim 8
Dependent Claim
20 words
The process of Claim 5 wherein said etching solution (2) is 10% HC1 and said light (5) wavelength is 6328R.
Claim 9
Dependent Claim
84 words
A process of providing self-alignment in a structure of the type wherein at least one electrode (9, 10) is positioned adjacent to but insulated from a second electrode (16) comprising the steps of masking the surface of a semiconductor member (3) to define a first electrode (9, 10), etching the region adjacent said masked electrode simultaneously, thereby providing, an undercut (13, 14) under said first electrode and employing both the vertical position and said undercut to define the position of said second electrode (16).
Claim 10
Dependent Claim
84 words
A process of providing self-alignment in a structure of the type wherein at least one electrode (9, 10) is positioned adjacent to but insulated from a second electrode (16) comprising the steps of masking the surface of a semiconductor member (3) to define a first electrode (9, 10), etching the region adjacent said masked electrode simultaneously, thereby providing, an undercut (13, 14) under said first electrode and employing both the vertical position and said undercut to define the position of said second electrode (16).
Claim 11
Dependent Claim
29 words
The process of Claim 7, wherein said first electrode is at least one of the source and drain of a MESFET transistor and said second electrode is the gate.
Claim 12
Dependent Claim
38 words
A MESFET self-aligned semiconductor structure, wherein the gate (15) is positioned by undercuts (13, 14) under the source and drain regions (9, 10; 11, 12), manufactured according to the process of anyone of the Claims 1 to 8.
Claim 13
Dependent Claim
136 words
A semiconductor device array in an active semiconductor region (3b) on a semiconductor substrate (3a) wafer having both enhancement mode and depletion mode field effect transistors comprising for each transistor device a source and a drain high conductivity electrode region (9-12; 9a-12a) positioned on said wafer (3) separated by a channel (16; 26), for each enhancement mode device an enhancement mode gate electrode (15) positioned in a photocurrent electrolytic etched region over said channel (16), the ends of said gate (15) being defined by undercuts (13, 14) beneath each said source and drain electrode region (9, 10; 11, 12), and for each depletion mode device a depletion mode gate electrode (15a) positioned on said channel (26) between said source and drain electrode region (9a, 10a; lla, 12a), and isolation between each said device in said array.
Claim 14
Dependent Claim
136 words
A semiconductor device array in an active semiconductor region (3b) on a semiconductor substrate (3a) wafer having both enhancement mode and depletion mode field effect transistors comprising for each transistor device a source and a drain high conductivity electrode region (9-12; 9a-12a) positioned on said wafer (3) separated by a channel (16; 26), for each enhancement mode device an enhancement mode gate electrode (15) positioned in a photocurrent electrolytic etched region over said channel (16), the ends of said gate (15) being defined by undercuts (13, 14) beneath each said source and drain electrode region (9, 10; 11, 12), and for each depletion mode device a depletion mode gate electrode (15a) positioned on said channel (26) between said source and drain electrode region (9a, 10a; lla, 12a), and isolation between each said device in said array.
References Cited (Backward Citations)
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