Microprocessor interface apparatus having a boot address relocator, a request pipeline, a prefetch queue, and an interrupt filter

Claim 1

A processor interface circuit, for coupling a microprocessor operating in tandem to an internal bus which handles requests for memory reads, memory writes, and input/output accesses issued by the microprocessor, the processor interface circuit comprising: a processor bus interface, which maintains a bidirectional data path over a processor bus between the microprocessor and the processor interface circuit; an internal bus interface, which maintains a bidirectional data path over the internal bus between the processor interface circuit and microprocessor request handlers internal to a processor system, said microprocessor request handlers including at least a memory interface circuit which reads and writes a memory in response to requests from the microprocessor; a boot address relocator, coupled to said processor bus interface such that said boot address relocator accesses an address portion of a memory access request, said boot address relocator for relocating an address in said address portion when a boot indicator is set and said address portion does not point to an address in said memory accessed by said memory interface circuit; a request pipeline, coupled to said processor bus interface and said internal bus interface, for accepting microprocessor requests and acknowledging said requests before said requests are output on said internal bus interface when said internal bus interface is not able immediately accept said requests; a prefetch queue, coupled to said processor bus interface and said internal bus interface, for fetching and holding a predicted block of data from said memory, said predicted block being a block in memory following a block which was requested by the microprocessor; and an interrupt filter, coupled to said internal bus interface and said processor bus interface, for receiving interrupt signals from said internal bus and passing on to the processor bus interrupts from a first class of interrupts, where said first class of interrupts have a present effect on program flow of the microprocessor, and storing interrupts from a second class of interrupts, where said second class of interrupts do not have a present effect on said program flow, until said stored interrupts would have an effect on said program flow, if at all.