Interrupt controller arrangement for mutually exclusive interrupt signals in data processing systems

Claim 2

In a data processing system, an interrupt controller arrangement comprising: (a) first and second encoding means respectively for generating first and second sets of encoded words corresponding to individual interrupt signals contained in first and second sets of interrupt signals, respectively, the first set of interrupt signals consisting of interrupt signals no two of which can occur simultaneously, and the second set containing at least two interrupt signals that can occur simultaneously; (b) a memory stack; and (c) multiplexing means for receiving the encoded first and second interrupt words from the first and second encoding means and for delivering to the memory stack during each time interval, of a prescribed sequence of time intervals, one of the encoded first words or one of the encoded second words depending upon the time interval.

Claim 3

The system of claim 1, further comprising write logic means for enabling the memory stack to be written with whichever word is being delivered to the stack by the multiplexing means during each such time interval if the corresponding interrupt signal has occurred within a prescribed amount of time prior to the time interval, including a separate latching means for recording the occurrences of each interrupt signal of the second set.

Claim 4

The system of claim 2, further comprising sources of the first and second groups of interrupt signals.

Claim 5

The system of claim 3, further comprising a synchronous microprocessor for receiving the encoded words from the memory stack.

Claim 6

The system of claim 1, further comprising sources of the interrupt signals of the first and second sets.

Claim 7

A data processing system comprising: (a) sources of first and second sets of interrupt signals, each of the signals being generated in response to the occurrence of a corresponding event in one of first and second sets of events, respectively, the first set consisting of events no two of which can occur simultaneously, and at least one of the interrupt signals of the second set being asynchronous with respect to the remaining signals of the second set; (b) first and second encoding means respectively for generating first and second sets of encoded words corresponding to individual ones of the interrupt signals of the first and second sets, respectively (c) a memory stack; (d) multiplexing means for receiving the encoded interrupt words of the first and second sets of words from the first and second encoding means and for alternatively delivering to the memory stack during each time interval of a prescribed sequence of time intervals an encoded word either of the first set or of the second set of encoded words depending upon the time interval; and (e) write logic means, including an array of latches, a separate latch for each interrupt signal of the second set of interrupt signals, each of the latches arranged for receiving and recording the occurrences of a different one of the interrupt signals of the second set of interrupt signals, said write logic means for enabling writing into the memory stack whatever word is being delivered to the stack by the multiplexing means during each such time interval if the corresponding interrupt signal has occurred since the last occasion that such word was delivered to the stack by the multiplexing means.

Claim 8

A data processing system comprising: (a) sources of first and second sets of interrupt signals, each of the signals being generated in response to the occurrence of a corresponding event in one of first and second sets of events, respectively, the first set consisting of events no two of which can occur simultaneously, and at least one of the interrupt signals of the second set being asynchronous with respect to the remaining signals of the second set; (b) first and second encoding means respectively for generating first and second sets of encoded words corresponding to individual ones of the interrupt signals of the first and second sets, respectively (c) a memory stack; (d) multiplexing means for receiving the encoded interrupt words of the first and second sets of words from the first and second encoding means and for alternatively delivering to the memory stack during each time interval of a prescribed sequence of time intervals an encoded word either of the first set or of the second set of encoded words depending upon the time interval; and (e) write logic means, including an array of latches, a separate latch for each interrupt signal of the second set of interrupt signals, each of the latches arranged for receiving and recording the occurrences of a different one of the interrupt signals of the second set of interrupt signals, said write logic means for enabling writing into the memory stack whatever word is being delivered to the stack by the multiplexing means during each such time interval if the corresponding interrupt signal has occurred since the last occasion that such word was delivered to the stack by the multiplexing means.

Claim 9

A data processing system comprising an interrupt controller arrangement including (a) a memory stack; (b) first and second data buses; (c) multiplexer means for delivering encoded to the memory stack alternately taken from the first and second data buses; (d) first and second encoders for delivering the encoded words encoded from first and second sets of words, respectively, to the first and second data buses, respectively, each word of the first and second sets representing respectively a corresponding interrupt signal, in which no two signals corresponding to the first set of words can occur simultaneously and in which the signals corresponding to the second set of words occur asynchronously with respect to each other; and (e) write logic for enabling the memory stack to be written with the encoded words being delivered to it by the multiplexer means if the corresponding interrupt signal has occurred within a prescribed period of time earlier and otherwise disabling the stack from being written.

Claim 10

A data processing system comprising an interrupt controller arrangement including (a) a memory stack; (b) first and second data buses; (c) multiplexer means for delivering encoded to the memory stack alternately taken from the first and second data buses; (d) first and second encoders for delivering the encoded words encoded from first and second sets of words, respectively, to the first and second data buses, respectively, each word of the first and second sets representing respectively a corresponding interrupt signal, in which no two signals corresponding to the first set of words can occur simultaneously and in which the signals corresponding to the second set of words occur asynchronously with respect to each other; and (e) write logic for enabling the memory stack to be written with the encoded words being delivered to it by the multiplexer means if the corresponding interrupt signal has occurred within a prescribed period of time earlier and otherwise disabling the stack from being written.