Interrupt control system

Claim 1

A data processing system under microinstruction control comprising: memory means for storing microinstruction sequences including an interrupt processing sequence comprising a first routine and a plurality of second routines, said first routine sequentially specifying polling of each of a plurality of first interrupt requests and each of a plurality of second interrupt requests in a predetermined order, and said second routines each specifying a processing of a respective one of said first and second interrupt requests; a plurality of first means each for generating one of said first interrupt requests; a plurality of second means each for generating one of said second interrupt requests; executing means provided on an integrated circuit chip including receiving means for receiving said second interrupt requests in parallel from said second means, status register means for manifesting mask bits, and gate means including a plurality of gates each connected to said receiving means and said status register means for masking one of said received second interrupt requests in response to a corresponding one of said mask bits; OR gate means for providing a single interrupt request signal in response to any of said first interrupt requests provided by said first means and in response to any of said masked interrupt requests provided by said gate means; control means formed on an integrated circuit chip for providing an initial address of said first routine to said memory means in response to said single interrupt request signal in order to initiate said first routine thereby; and means connected to said gate means and said first means for generating a jump signal and applying said jump signal to said memory means during the polling of said first and second interrupt requests by said first routine when a specified interrupt request is provided thereto, said jump signal ordering said memory means to jump to the one of said second routines corresponding to the specified interrupt request; wherein said OR gate means comprises first and second OR gate means, said first OR gate means being provided outside of said integrated circuit chip on which said executing means is provided and outside of said integrated circuit chip on which said control means is provided, said second OR gate means being provided within the same integrated circuit chip as said executing means, said first OR gate means being responsive to any of said generated first interrupt requests, said second OR gate means being responsive to any of said masked second interrupt requests, and said first and second OR gate means being mutually connected so that each of the outputs thereof is provided to said control means as said single interrupt request signal via a common signal line.