Pipelined digital CPU with deadlock resolution

Claim 2

A processor comprising: (a) a plurality of execution stages connected in sequence and a plurality of memory access stages connected in sequence; (b) microinstruction means for producing microinstructions for controlling the operation of said execution and memory access stages; (c) a plurality of latches receiving output from said microinstruction means, said plurality of latches temporarily storing controls representing said microinstructions, a respective one of said plurality of latches being associated separately with each one of said stages, said controls being separately coupled from each of said latches to each one of said stages; (d) means for advancing said controls through said plurality of latches for execution stages, and separate means for advancing said controls through said plurality of latches for said memory access stages, said separate means including means for applying said controls to a last one of said plurality of latches for said memory access stages under a selected condition whereby said memory access stages can complete a memory access operation even if said execution stages are stalled.

Claim 3

A processor according to claim 1 wherein said microinstruction means includes a control store, and said microinstructions include sets of control bits read from said control store, and said controls stored in said latches are derived from said sets of control bits of said microinstructions.

Claim 4

A processor according to claim 1 wherein said means for advancing for said execution stages and said means for advancing for said memory access stages both include clocking means.

Claim 5

A processor according to claim 3 wherein said clocking means includes conditional clocking means and unconditional clocking means.

Claim 6

A processor according to claim 4 wherein said conditional clocking means are in early ones of said stages and said unconditional clocking means are in later ones of said stages.

Claim 7

A processor comprising: (a) a plurality of first type stages connected in sequence and a plurality of second type stages connected in sequence, each of said first type stages performing processor execution functions and each of said second type stages performing memory access functions; (b) means for producing sets of control bits for controlling the operation of each of said first and second type stages; (c) a plurality of storage means for temporarily storing said sets of control bits, a respective one of said plurality of storage means being separately associated with each one of said first and second type stages; (d) first means for advancing said control bits through said plurality of storage means for said first type stages, and second means for advancing said control bits through said plurality of storage means for said second type stages, wherein said first and second means are separately controlled, said second means including means for applying said control bits to a last one of said plurality of storage means for said second type of stages under a selected condition of operation so that the second means can continue advancing while said first means and a first part of said second means are stalled.

Claim 8

A processor comprising: (a) a plurality of first type stages connected in sequence and a plurality of second type stages connected in sequence, each of said first type stages performing processor execution functions and each of said second type stages performing memory access functions; (b) means for producing sets of control bits for controlling the operation of each of said first and second type stages; (c) a plurality of storage means for temporarily storing said sets of control bits, a respective one of said plurality of storage means being separately associated with each one of said first and second type stages; (d) first means for advancing said control bits through said plurality of storage means for said first type stages, and second means for advancing said control bits through said plurality of storage means for said second type stages, wherein said first and second means are separately controlled, said second means including means for applying said control bits to a last one of said plurality of storage means for said second type of stages under a selected condition of operation so that the second means can continue advancing while said first means and a first part of said second means are stalled.

Claim 9

A processor according to claim 6 wherein said first type stages are execution stages for selecting operands, performing functions on said operands, and storing the results of said operations.

Claim 10

A processor according to claim 7 wherein said second type stages are memory access stages for accessing memory locations for reading or writing operands or results to or from said execution stages.

Claim 11

A processor according to claim 6 wherein said means for producing sets of control bits includes a control store, and said sets of control bits are included in microinstructions read from said control store.

Claim 12

A processor according to claim 6 wherein said first and second type stages are pipelined stages and said storage means are latches for storing said control bits.

Claim 15

A method according to claim 11 wherein said first type stages are execution stages for selecting operands, performing functions on said operands, and storing the results of said operations.

Claim 16

A method according to claim 13 wherein said second type stages are memory access stages for accessing memory locations for reading or writing operands or results to or from said execution stages.

Claim 17

A method according to claim 11 wherein said sets of control bits are microinstructions read from a control store.

Claim 18

A method according to claim 11 wherein said first and second type stages are pipelined stages and said storage means are latches for storing said control bits.

Claim 19

A pipelined processor comprising: (a) an execution unit having a plurality of sequentially-coupled execution stages including a first stage for accessing operands from local registers, a second stage for performing operations on said operands, and a third stage for storing results of said operations; (b) a memory interface unit having a plurality of sequentially-coupled memory-interface stages including a first stage for calculating memory requests, a second stage for evaluating memory availability, and a third stage for issuing memory addresses for memory access and receiving data from memory if available. (c) means for generating sets of control bits, one set for each cycle of operation of said processor, and (i) first means having an input connected to said means for generating and having outputs connected to said execution stages for applying at least some of each one of said sets of control bits to each of said first, second and third stages of said execution unit in successive ones of said machine cycles. (ii) second means having an input connected to said means for generating and having outputs connected to said memory-interface stages for applying at least some of each one of said sets of control bits to each of said first, second and third stages of said memory interface unit in successive ones of said machine cycles, (d) clocking means connected to said first and second means to advance said sets of control bits to said first, second and third stages of said execution unit and said memory interface unit in synchronization during normal operation of said processor and for stalling advance of said control bits to at least said first and second stages of said execution unit and said memory interface unit in a stall condition if a selected condition of operation occurs, said clocking means functioning to separately advance said sets of control bits for at least one of the stages of said memory interface unit during said stall condition if said selected condition of operation occurs.

Claim 20

A pipelined processor comprising: (a) an execution unit having a plurality of sequentially-coupled execution stages including a first stage for accessing operands from local registers, a second stage for performing operations on said operands, and a third stage for storing results of said operations; (b) a memory interface unit having a plurality of sequentially-coupled memory-interface stages including a first stage for calculating memory requests, a second stage for evaluating memory availability, and a third stage for issuing memory addresses for memory access and receiving data from memory if available. (c) means for generating sets of control bits, one set for each cycle of operation of said processor, and (i) first means having an input connected to said means for generating and having outputs connected to said execution stages for applying at least some of each one of said sets of control bits to each of said first, second and third stages of said execution unit in successive ones of said machine cycles. (ii) second means having an input connected to said means for generating and having outputs connected to said memory-interface stages for applying at least some of each one of said sets of control bits to each of said first, second and third stages of said memory interface unit in successive ones of said machine cycles, (d) clocking means connected to said first and second means to advance said sets of control bits to said first, second and third stages of said execution unit and said memory interface unit in synchronization during normal operation of said processor and for stalling advance of said control bits to at least said first and second stages of said execution unit and said memory interface unit in a stall condition if a selected condition of operation occurs, said clocking means functioning to separately advance said sets of control bits for at least one of the stages of said memory interface unit during said stall condition if said selected condition of operation occurs.

Claim 21

A processor according to claim 16 wherein said clocking means unconditionally advances a set of control bits to said third stages even when said stall condition of operation exists.

Claim 22

A processor according to claim 17 wherein said clocking means causes a no-operation set of control bits to be inserted to said third stage of said execution unit during said stall condition of operation.

Claim 23

A processor according to claim 16 wherein said clocking means separately advances said set of control bits to said second stage of said memory interface unit during said stall condition of operation.

Claim 24

A processor according to claim 19 wherein separate advancing is done when there is a stall condition of operation and also a deadlock condition of operation.