Microprocessor for evaluating an application system

Claim 2

The microprocessor as set forth in claim 1, wherein: said microprocessor is provided with a user terminal and is constructed on a single chip.

Claim 3

The microprocessor as set forth in claim 2, wherein: said microprocessor is further provided with a tool terminal coupled to an evaluation tool.

Claim 4

The microprocessor as set forth in claim 1, wherein: said hold request signal issued from said external unit is applied at a time when an address signal issued from said microprocessor coincides with a set address.

Claim 5

A microprocessor comprising: an instruction prefetch means (2, 110) for prefetching an instruction issued form an external unit to store a plurality of said instructions; an instruction prefetch control means (3, 120) which issues a fetch address output signal (6) to said external unit when said instructions are prefetched, and issues a read control signal (7, 200) for reading said instructions to said instruction prefetch means (2, 110) when said instructions are read out; an instruction execution means (4, 140) for executing said instructions read out of said instruction prefetch means (2, 110); and a hold control means (5, 130) which, upon receipt of said read control signal (7, 200) and a hold request signal (8, 201) issued from said external unit, issues to said instruction execution means (4, 140) an instruction halt signal (9, 202) for halting the execution of one of said instructions before said one of said instructions is executed, said instructions being stored in said instruction prefetch means (2, 110).

Claim 6

The microprocessor as set forth in claim 5, wherein; said instruction prefetch means (2, 110) is provided with a set of first registers of n pieces for prefetching said instructions; and said hold control means (5, 130) is provided with a set of second registers of n pieces corresponding to said first registers of n pieces in a one-to-one correlation, each of said second registers being a one-bit type register for storing said hold request signal (8, 201) therein.

Claim 7

The microprocessor as set forth in claim 6, wherein: said instruction means (2, 110) is provided with both a write pointer and a read pointer; according to said write pointer, said first and said second registers prefetch said instructions, and store said hold request signal (8, 201) therein; and according to said read pointer, said prefetched instructions and said stored hold request signal (8, 201 ) are issued to said instruction execution means ( 4, 140 ).

Claim 8

In a microprocessor which prefetches instructions in sequence to sequentially execute said instructions, an improvement wherein; means for issuing a hold request signal from an external unit in correspondence with the prefetch of said instructions; means for halting said execution of said prefetched instructions when said corresponding hold request signal is fetched during the execution of said prefetched instructions.