Protection circuit which prevents avalanche breakdown in a fet by having a floating substrate and a voltage controlled gate

Claim 2

A transistor circuit comprising: a MOS transistor having a control gate, a source, a drain and an open back gate; control means for controlling a voltage applied to said control gate of said MOS transistor, said control means controlling an avalanche breakdown voltage of a parasitic bipolar transistor formed by said drain, said back gate and said source of said MOS transistor.

Claim 3

The transistor circuit according to claim 1, wherein a channel passage of said MOS transistor has a first end connected to a power supply electrode, and a second end connected to a signal line.

Claim 4

The transistor circuit according to claim 1, wherein said voltage applied to said control gate by said control means is variable.

Claim 5

A transistor circuit comprising: a first MOS transistor having a control gate, a source, a drain and an open back gate; surge detecting means, connected to said control gate of said first MOS transistor, for detecting a surge voltage and applying a voltage, according to said detected surge voltage, to said control gate of first said MOS transistor, said surge detecting means controlling an avalanche breakdown voltage of a parasitic bipolar transistor formed by said drain, said back gate and said source of said first MOS transistor.

Claim 6

A transistor circuit comprising: a first MOS transistor having a control gate, a source, a drain and an open back gate; surge detecting means, connected to said control gate of said first MOS transistor, for detecting a surge voltage and applying a voltage, according to said detected surge voltage, to said control gate of first said MOS transistor, said surge detecting means controlling an avalanche breakdown voltage of a parasitic bipolar transistor formed by said drain, said back gate and said source of said first MOS transistor.

Claim 7

The transistor circuit according to claim 4, wherein said surge detecting means comprises a bipolar transistor and a resistor between a base of said bipolar transistor and a power supply electrode, one of a collector and emitter of said bipolar transistor and a first end of a channel passage of said first MOS transistor being connected to an external terminal of an integrated circuit including said first MOS transistor and said surge detecting means, and the other one of said collector and emitter of said bipolar transistor and a second end of said channel passage of said first MOS transistor being connected to said power supply electrode.

Claim 8

The transistor circuit according to claim 5, wherein said surge detecting means includes a parasitic bipolar transistor of a second MOS transistor, and said parasitic bipolar transistor is used as said bipolar transistor of said surge detecting means.

Claim 9

A transistor circuit comprising: a first MOS transistor having a control gate, a source, a drain and an open back gate; first surge detecting means, connected to said control gate of said first MOS transistor, for detecting a surge voltage and applying a voltage, according to said detected surge voltage, to said control gate of said first MOS transistor, said first surge detecting means including a first bipolar transistor and a first resistor between a base of said first bipolar transistor and a first power supply electrode, one of a collector and emitter of said first bipolar transistor and a first end of a channel passage of said first MOS transistor being connected to an external terminal of an integrated circuit including said first MOS transistor and said surge detecting means, and the other one of said collector and emitter of said first bipolar transistor and a second end of said channel passage of said first MOS transistor being connected to said first power supply electrode; a second MOS transistor having a control gate, a source, a drain and an open back gate; second surge detecting means, connected to said control gate of said second MOS transistor, for detecting said surge voltage and applying a voltage, according to said surge voltage detected by said second surge detecting means, to said control gate of said second MOS transistor, said second surge detecting means including a second bipolar transistor and a second resistor between a base of said second bipolar transistor and a second power supply electrode, one of a collector and emitter of said second bipolar transistor and a first end of a channel passage of said second MOS transistor being connected to said external terminal of said integrated circuit, and the other one of said collector and emitter of said second bipolar transistor and a second end of said channel passage of said second MOS transistor being connected to said second power supply electrode, said first and second surge detecting means respectively controlling avalanche breakdown voltages of parasitic bipolar transistors formed by said drains, said back gates and said sources of said first and second MOS transistors.

Claim 10

A transistor circuit comprising: a first MOS transistor having a control gate, a source, a drain and an open back gate; first surge detecting means, connected to said control gate of said first MOS transistor, for detecting a surge voltage and applying a voltage, according to said detected surge voltage, to said control gate of said first MOS transistor, said first surge detecting means including a first bipolar transistor and a first resistor between a base of said first bipolar transistor and a first power supply electrode, one of a collector and emitter of said first bipolar transistor and a first end of a channel passage of said first MOS transistor being connected to an external terminal of an integrated circuit including said first MOS transistor and said surge detecting means, and the other one of said collector and emitter of said first bipolar transistor and a second end of said channel passage of said first MOS transistor being connected to said first power supply electrode; a second MOS transistor having a control gate, a source, a drain and an open back gate; second surge detecting means, connected to said control gate of said second MOS transistor, for detecting said surge voltage and applying a voltage, according to said surge voltage detected by said second surge detecting means, to said control gate of said second MOS transistor, said second surge detecting means including a second bipolar transistor and a second resistor between a base of said second bipolar transistor and a second power supply electrode, one of a collector and emitter of said second bipolar transistor and a first end of a channel passage of said second MOS transistor being connected to said external terminal of said integrated circuit, and the other one of said collector and emitter of said second bipolar transistor and a second end of said channel passage of said second MOS transistor being connected to said second power supply electrode, said first and second surge detecting means respectively controlling avalanche breakdown voltages of parasitic bipolar transistors formed by said drains, said back gates and said sources of said first and second MOS transistors.

Claim 11

The transistor circuit according to claim 7, wherein said first and second surge detecting means respectively include parasitic bipolar transistors of third and fourth MOS transistors, and said parasitic bipolar transistors are respectively used as said first and second bipolar transistors.