CMOS power-on reset circuit using hysteresis

Claim 2

A CMOS power-on reset circuit for generating a reset signal in response to the activation of a power supply voltage, said reset circuit comprising: a power supply terminal (18) for receiving a power supply voltage (VDD); voltage clamping means (14) responsive to said power supply voltage (VDD) for generating a first control voltage; said voltage clamping means including an N-channel transistor (M1), a first resistor (R1), and a second resistor (R2); said first resistor having its one end connected to the power supply terminal and its other end connected to one end of said second resistor at a first internal node (A) to provide the first control voltage, said N-channel transistor (M1) having its drain and gate electrodes connected together and to the other end of said second resistor, said N-channel transistor (M1) having its source electrode connected to a ground potential (VSS); and hysteresis switching means responsive to said power supply voltage (VDD) and said first control voltage for generating a second control voltage which is used to turn off a reset signal at an output node when a first predetermined trip level has been exceeded and for turning on said reset signal when a second predetermined trip level has been reached which is lower than said first predetermined trip level.

Claim 3

A reset circuit as claimed in claim 1, wherein said hysteresis switching means includes a P-channel pull-up transistor (M2), a first N-channel pull-down transistor (M3), a current-source transistor (M4), a second N-channel pull-down transistor (M5), and an inverter (G1).

Claim 4

A reset circuit as claimed in claim 2, wherein said P-channel transistor (M2) has its source electrode connected to the power supply terminal (18), its gate electrode connected to the first internal node (A), and its drain electrode connected to a second internal node (C) to provide the second control signal, said first N-channel pull-down transistor (M3) having its drain electrode connected to the second internal node (C) and its gate electrode connected to the first internal node (A), said current-source transistor (M4) having its drain electrode connected to the source of said first N-channel pull-down transistor (M3), its gate electrode connected to the output of said inverter (G1), and its source electrode connected to the ground potential (VSS), said second N-channel pull-down transistor (M5) having its drain connected to the second internal node (C), its gate electrode connected to the first internal node (A), and its source electrode connected to the ground potential, said inverter (G1) having its input connected also to the second internal node (C) and its output connected to the output terminal (12) to provide the reset signal.

Claim 5

A reset circuit as claimed in claim 3, further comprising at least one of logic and memory devices (13) being formed on a single monolithic semiconductor integrated circuit chip (15) and being responsive to said reset signal.

Claim 6

A reset circuit as claimed in claim 4, wherein said reset circuit (10) is formed as a part of the same integrated circuit chip (15) containing the at least one of logic and memory devices (13).

Claim 7

A reset circuit as claimed in claim 1, further comprising at least one of logic and memory devices (13) being formed on a single monolithic semiconductor integrated circuit chip (15) and being responsive to said reset signal.

Claim 8

A reset circuit as claimed in claim 6, wherein said reset circuit (10) is formed as a part of the same integrated circuit chip (15) containing the at least one of logic and memory devices (13).

Claim 9

A CMOS power-on reset circuit for generating a reset signal in response to the activation of a power supply voltage, said reset circuit comprising: a power supply terminal (18) for receiving a power supply voltage (VDD); voltage clamping means (14) responsive to said power supply voltage (VDD) for generating a first control voltage; said voltage clamping means including an N-channel transistor (M1), a first resistor (R1), and a second resistor (R2); said first resistor having its one end connected to the power supply terminal and its other end connected to one end of said second resistor at a first internal node (A) to provide the first control voltage, said N-channel transistor (M1) having its drain and gate electrodes connected together and to the other end of said second resistor, said N-channel transistor (M1) having its source electrode connected to a ground potential (VSS); hysteresis switching means responsive to said power supply voltage (VDD) and said first control voltage for generating a second control voltage which is used to turn off a reset signal at an output node when a first predetermined trip level has been exceeded and for turning on said reset signal when a second predetermined trip level has been reached which is lower than said first predetermined trip level; said hysteresis switching means including a P-channel pull-up transistor (M2), a first N-channel pull-down transistor (M3), a current-source transistor (M4), a second N-channel pull-down transistor (M5), and an inverter (G1); said P-channel transistor (M2) having its source electrode connected to the power supply terminal (18), its gate electrode connected to the first internal node (A), and its drain electrode connected to a second internal node (C) to provide the second control signal, said first N-channel pull-down transistor (M3) having its drain electrode connected to the second internal node (C) and its gate electrode connected to the first internal node (A), said current-source transistor (M4) having its drain electrode connected to the source of said first N-channel pull-down transistor (M3), its gate electrode connected to the output of said inverter (G1), and its source electrode connected to the ground potential (VSS), said second N-channel pull-down transistor (M5) having its drain connected to the second internal node (C), its gate electrode connected to the first internal node (A), and its source electrode connected to the ground potential, said inverter (G1) having its input connected also to the second internal node (C) and its output connected to the output terminal (12) to provide the reset signal; and logic and/or memory devices (13) operatively connected to the power supply voltage and said reset signal and being responsive thereto.

Claim 10

A CMOS power-on reset circuit for generating a reset signal in response to the activation of a power supply voltage, said reset circuit comprising: a power supply terminal (18) for receiving a power supply voltage (VDD); voltage clamping means (14) responsive to said power supply voltage (VDD) for generating a first control voltage; said voltage clamping means including an N-channel transistor (M1), a first resistor (R1), and a second resistor (R2); said first resistor having its one end connected to the power supply terminal and its other end connected to one end of said second resistor at a first internal node (A) to provide the first control voltage, said N-channel transistor (M1) having its drain and gate electrodes connected together and to the other end of said second resistor, said N-channel transistor (M1) having its source electrode connected to a ground potential (VSS); hysteresis switching means responsive to said power supply voltage (VDD) and said first control voltage for generating a second control voltage which is used to turn off a reset signal at an output node when a first predetermined trip level has been exceeded and for turning on said reset signal when a second predetermined trip level has been reached which is lower than said first predetermined trip level; said hysteresis switching means including a P-channel pull-up transistor (M2), a first N-channel pull-down transistor (M3), a current-source transistor (M4), a second N-channel pull-down transistor (M5), and an inverter (G1); said P-channel transistor (M2) having its source electrode connected to the power supply terminal (18), its gate electrode connected to the first internal node (A), and its drain electrode connected to a second internal node (C) to provide the second control signal, said first N-channel pull-down transistor (M3) having its drain electrode connected to the second internal node (C) and its gate electrode connected to the first internal node (A), said current-source transistor (M4) having its drain electrode connected to the source of said first N-channel pull-down transistor (M3), its gate electrode connected to the output of said inverter (G1), and its source electrode connected to the ground potential (VSS), said second N-channel pull-down transistor (M5) having its drain connected to the second internal node (C), its gate electrode connected to the first internal node (A), and its source electrode connected to the ground potential, said inverter (G1) having its input connected also to the second internal node (C) and its output connected to the output terminal (12) to provide the reset signal; and logic and/or memory devices (13) operatively connected to the power supply voltage and said reset signal and being responsive thereto.

Claim 11

A reset circuit as claimed in claim 8, further comprising at least one of logic and memory devices (13) being formed on a single monolithic semiconductor integrated circuit chip (15).

Claim 12

A reset circuit as claimed in claim 9, wherein said reset circuit (10) is formed as a part of the same integrated circuit chip (15) containing the at least one of logic and memory devices (13).