Initialization circuit for memory registers

Claim 2

An initialization circuit for memory registers, comprising: a signal input terminal for receiving a supply voltage, the supply voltage increasing from a null voltage upon initialization; a first initialization circuit portion connected to the signal input terminal, the first initialization circuit portion producing a first initialization voltage in response to the supply voltage, the first initialization voltage being proportional to the supply voltage when the supply voltage is below a predetermined tripping value and being a null voltage when the supply voltage exceeds the tripping value; a second initialization circuit portion for producing a second initialization voltage in response to the supply voltage, the second initialization voltage being proportional to the supply voltage until the supply voltage exceeds a second tripping value, the second initialization voltage being equal to a null voltage thereafter; a first output terminal connected to the first initialization circuit portion for providing a first output voltage corresponding to the first initialization voltage; and a second output terminal connected to the second initialization circuit portion for providing a second output voltage corresponding to the second initialization voltage.

Claim 3

The circuit of claim 1 wherein the second tripping value is different from the first tripping value.

Claim 4

The circuit of claim 1 wherein the second tripping value is equal to the first tripping value.

Claim 5

The circuit of claim 1 wherein after the supply voltage exceeds the second tripping value the second initialization voltage remains at the null voltage unless the supply voltage equals the null voltage after having exceeded the second tripping value.

Claim 6

A circuit according to claim 4, wherein said second initialization circuit portion comprises a pair of inverters in a cross-connection feedback relationship with each other, each pair of inverters being connected to receive the first initialization voltage at a respective input terminal.

Claim 7

A circuit according to claim 5, characterized in that each of said inverters comprises a pair of MOS transistors of the P-channel and N-channel types, respectively, wherein a drain terminal of each of the P-channel transistors is connected to a drain terminal of its corresponding N-channel transistor at a drain-to-drain contact point and a gate terminal of each of the transistors in the first pair of transistors is connected to the point of drain-to-drain contact of the second pair of transistors, and a gate terminal of each of the transistors in the second pair of transistors is connected to the point of drain-to-drain contact of the first pair of transistors.

Claim 8

A circuit according to claim 5, characterized in that said inverters are unbalanced inverters having different tripping voltages.

Claim 9

A circuit according to claim 4, wherein the first initialization circuit portion comprises: a pair of MOS transistors connected in series between the gate terminal of the first MOS transistor and ground; an RC circuit connected in parallel between said gate of the first MOS transistor and said signal input terminal; and a second RC circuit connected in parallel between the drain of the first MOS transistor and ground, and at least one inverter connected intermediate said drain of said first MOS transistor and said first output terminal.

Claim 10

A circuit according to claim 8, comprising three inverters serially connected between said drain of said first MOS transistor and said first output terminal.

Claim 11

A circuit according to claim 8, characterized in that the drain of said first MOS transistor is also connected to the gate of a fourth MOS transistor having its source terminal connected to ground and its drain terminal connected to the second output terminal through at least one inverter.

Claim 12

A circuit according to claim 10, characterized in that two serial inverters are connected between the drain terminal of the fourth transistor and said second output terminal.

Claim 13

A circuit according to claim 8, characterized in that said first MOS transistor is a P-channel MOS type.

Claim 14

A circuit according to claim 12, characterized in that said fourth transistor is an N-channel MOS type.

Claim 15

A circuit for electrical initialization, comprising: an initialization circuit portion for producing a first initialization output voltage, the initialization circuit portion having a supply voltage input terminal for receiving a supply voltage and a voltage output terminal, the first initialization output voltage being proportional to the supply voltage at supply voltage levels below a threshold voltage and the first initialization output voltage being equal to a null voltage at supply voltage levels above the threshold voltage; an output driver portion connected to the output terminal of the initialization circuit portion, the output driver portion having an output terminal and producing a voltage proportional to the first initialization output voltage at the output terminal; and a second circuit portion connected to the first voltage output terminal, the second circuit portion having a second initialization output terminal and producing a second initialization output voltage at the second initialization output terminal upon application of a supply voltage to the supply voltage input terminal, the second initialization output voltage being proportional to the supply voltage upon an initial application of the supply voltage until the supply voltage reaches the threshold voltage and the second initialization output voltage being a null voltage thereafter.

Claim 16

A circuit for electrical initialization, comprising: an initialization circuit portion for producing a first initialization output voltage, the initialization circuit portion having a supply voltage input terminal for receiving a supply voltage and a voltage output terminal, the first initialization output voltage being proportional to the supply voltage at supply voltage levels below a threshold voltage and the first initialization output voltage being equal to a null voltage at supply voltage levels above the threshold voltage; an output driver portion connected to the output terminal of the initialization circuit portion, the output driver portion having an output terminal and producing a voltage proportional to the first initialization output voltage at the output terminal; and a second circuit portion connected to the first voltage output terminal, the second circuit portion having a second initialization output terminal and producing a second initialization output voltage at the second initialization output terminal upon application of a supply voltage to the supply voltage input terminal, the second initialization output voltage being proportional to the supply voltage upon an initial application of the supply voltage until the supply voltage reaches the threshold voltage and the second initialization output voltage being a null voltage thereafter.

Claim 17

The circuit of claim 14, wherein the second circuit portion further includes: an opposing inverter pair, including a pair of inverters in a cross-connection feedback configuration, the opposing inverter pair connected electrically between the first voltage output terminal and an output driver portion of the second circuit portion.

Claim 18

The circuit of claim 15 wherein each of said inverters comprises a pair of MOS transistors of the P-channel and N-channel types.

Claim 19

The circuit of claim 15 wherein the first inverter has a first inverter tripping voltage and the second inverter has a second inverter tripping voltage, the first inverter tripping voltage being different from the second inverter tripping voltage.

Claim 20

The circuit of claim 14, wherein the first initialization portion includes: a primary transistor having a gate terminal, drain terminal, and source terminal, the source of the primary transistor being connected electrically to the supply voltage input and the drain of the primary transistor being connected electrically to the first initialization output terminal; a parallel circuit, including a resistor and capacitor connected in parallel, the parallel circuit being connected electrically between the source of the primary transistor and the gate of the primary transistor; a triggering transistor pair serially electrically connected between the gate of the primary transistor and ground; and a second parallel circuit, including a resistor and capacitor in parallel, the second parallel circuit being electrically connected in parallel between the drain of the primary transistor and ground.

Claim 21

The circuit of claim 18 wherein the second circuit portion includes: a second primary transistor having a second primary gate, second primary drain, and second primary source, the gate of the second primary transistor being connected electrically to the first initialization output terminal, the second primary source being connected electrically to ground and the second primary drain being connected electrically to a second initialization portion output; and an unbalanced inverter pair having an inverter pair input, an inverter pair output and an inverter pair reference, the inverter pair input being connected electrically to the supply voltage input, the inverter pair reference being connected electrically to ground and the inverter pair output being connected electrically to the second primary drain.

Claim 22

An initialization circuit for memory registers, comprising: a signal input terminal for receiving a supply voltage, the supply voltage increasing from a null voltage upon initialization; a first initialization circuit portion connected to the signal input terminal, the first initialization circuit portion producing a first initialization voltage in response to the supply voltage, the first initialization voltage being proportional to the supply voltage when the supply voltage is below a predetermined first tripping value and being a null voltage when the supply voltage exceeds the tripping value; a second initialization circuit portion connected to receive the first initialization voltage from the first initialization circuit portion, the second initialization circuit portion producing a second initialization voltage in response to the first initialization voltage, the second initialization voltage being proportional to the first initialization voltage until the first initialization voltage exceeds a second tripping value, the second initialization voltage being equal to a null voltage thereafter unless the supply voltage equals the null voltage after having exceeded the second tripping value; a first output terminal connected to the first initialization circuit portion for providing a first output voltage corresponding to the first initialization voltage; and a second output terminal connected to the second initialization circuit portion for providing a second output voltage corresponding to the second initialization voltage.

Claim 23

An initialization circuit for memory registers, comprising: a signal input terminal for receiving a supply voltage, the supply voltage increasing from a null voltage upon initialization; a first initialization circuit portion connected to the signal input terminal, the first initialization circuit portion producing a first initialization voltage in response to the supply voltage, the first initialization voltage being proportional to the supply voltage when the supply voltage is below a predetermined first tripping value and being a null voltage when the supply voltage exceeds the tripping value; a second initialization circuit portion connected to receive the first initialization voltage from the first initialization circuit portion, the second initialization circuit portion producing a second initialization voltage in response to the first initialization voltage, the second initialization voltage being proportional to the first initialization voltage until the first initialization voltage exceeds a second tripping value, the second initialization voltage being equal to a null voltage thereafter unless the supply voltage equals the null voltage after having exceeded the second tripping value; a first output terminal connected to the first initialization circuit portion for providing a first output voltage corresponding to the first initialization voltage; and a second output terminal connected to the second initialization circuit portion for providing a second output voltage corresponding to the second initialization voltage.