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Patent US5532964A successfully refreshed from Google Patents.
US5532964A
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US
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Method and circuit for simultaneously programming and verifying the programming of selected EEPROM cells
Assignee: SanDisk Technologies LLC
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Filing: 1995-05-04
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Granted: 1996-07-02
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Expires: 2015-05-04
Abstract
Abstract A method and circuit programs and automatically verifies the programming of selected EEPROM cells without alternating between programming and reading modes like prior art methods and circuitry. The circuitry includes a programming circuit and a bit line voltage regulation circuit. The programming circuit further includes a novel sense amplifier which unlike prior art sense amplifiers, is operable during both cell reading and programming modes. Included in the sense amplifier are two current providing circuits. A first circuit provides current to a selected EEPROM cell which is sufficient for reading the programmed state of the cell, and a second circuit which automatically provides additional current when required, for programming the cell. The sense amplifier detects when programming of a selected EEPROM cell has completed and causes programming of that cell to be terminated. The voltage regulation circuitry regulates the bit line voltage to the selected EEPROM cell's drain electrode. The programming circuitry, including the sense amplifier, and voltage regulation circuitry are shown to be shared between a plurality of bit lines through a bit line selection circuit.
Inventors
- 👤 Raul-Adrian Cernea
- 👤 Sanjay Mehrotra
- 👤 Douglas J. Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 04:41
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3436; G11C16/3468; G11C16/3486; G11C16/10; G11C16/12; G11C16/3481
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
209 words
An EEPROM having a plurality of memory cells respectively connected to a plurality of bit lines, and a bit line selection circuit including a plurality of switches having a plurality of control inputs connected to a plurality of bit line selection signals, a plurality of outputs connected to said plurality of bit lines, and a sense line input connected through said plurality of switches to a selected one of said plurality of bit lines by respectively turning on or off each of said plurality of switches as determined by said plurality of bit line selection signals, said EEPROM further including a voltage regulator circuit comprising: a n-mos transistor having a drain electrode connected to a voltage supply, a source electrode connected to said sense line input of said selection circuit, and a control gate; and a differential amplifier having a first input connected to a reference voltage, a second input directly connected to said selected one of said plurality of bit lines, and an output, proportional to a difference between said first and second inputs, connected to said control gate of said n-mos transistor so that a bit line voltage on said selected one of said plurality of bit lines is maintained to be equal to said reference voltage.
Claim 2
Dependent Claim
209 words
An EEPROM having a plurality of memory cells respectively connected to a plurality of bit lines, and a bit line selection circuit including a plurality of switches having a plurality of control inputs connected to a plurality of bit line selection signals, a plurality of outputs connected to said plurality of bit lines, and a sense line input connected through said plurality of switches to a selected one of said plurality of bit lines by respectively turning on or off each of said plurality of switches as determined by said plurality of bit line selection signals, said EEPROM further including a voltage regulator circuit comprising: a n-mos transistor having a drain electrode connected to a voltage supply, a source electrode connected to said sense line input of said selection circuit, and a control gate; and a differential amplifier having a first input connected to a reference voltage, a second input directly connected to said selected one of said plurality of bit lines, and an output, proportional to a difference between said first and second inputs, connected to said control gate of said n-mos transistor so that a bit line voltage on said selected one of said plurality of bit lines is maintained to be equal to said reference voltage.
Claim 3
Dependent Claim
51 words
The EEPROM as recited in claim 1, wherein said voltage regulator circuit regulates said voltage on said selected one of said plurality of bit lines at a node located between said bit line selection circuit and an EEPROM memory cell connected to said selected one of said plurality of bit lines.
Claim 4
Dependent Claim
338 words
An EEPROM having a plurality of memory cells, each memory cell having a control gate, a drain electrode, and a source electrode, wherein a selected one of said plurality of memory cells has its control gate connected to a word line, its source electrode connected to a first bit line, and its drain electrode connected to a second bit line, said selected one memory cell being accessed by providing appropriate voltages to said word line, first bit line, and second bit line, and wherein said selected one memory cell draws through said second bit line, a first current, if said selected one memory cell is in an unprogrammed state, or a second current less than said first current, if said selected one memory cell is in a programmed state, said EEPROM including a voltage regulator circuit comprising: a first n-mos transistor having a drain electrode connected to a voltage supply, a source electrode connected to said second bit line having a bit line voltage, and a control gate; a first p-mos transistor having a source electrode connected to said voltage supply, a drain electrode and a control gate, wherein said drain electrode of said first p-mos transistor is connected to said control gate of said first p-mos transitor; a second p-mos transistor having a source electrode connected to said voltage supply, a drain electrode connected to the control gate of said first n-mos transistor, and a control gate connected to the control gate of said first p-mos transistor; a second n-mos transistor having a drain electrode connected to the source electrode of said first p-mos transistor, a control gate connected to a voltage reference, and a source connected to a current sink; and a plurality of n-mos transistors, each having a drain electrode connected to the drain of said second p-mos transistor, a source electrode connected to said current sink, and a control gate connected to one of a plurality of bit lines, wherein each of said plurality of bit lines is connected to a corresponding memory cell.
Claim 5
Dependent Claim
338 words
An EEPROM having a plurality of memory cells, each memory cell having a control gate, a drain electrode, and a source electrode, wherein a selected one of said plurality of memory cells has its control gate connected to a word line, its source electrode connected to a first bit line, and its drain electrode connected to a second bit line, said selected one memory cell being accessed by providing appropriate voltages to said word line, first bit line, and second bit line, and wherein said selected one memory cell draws through said second bit line, a first current, if said selected one memory cell is in an unprogrammed state, or a second current less than said first current, if said selected one memory cell is in a programmed state, said EEPROM including a voltage regulator circuit comprising: a first n-mos transistor having a drain electrode connected to a voltage supply, a source electrode connected to said second bit line having a bit line voltage, and a control gate; a first p-mos transistor having a source electrode connected to said voltage supply, a drain electrode and a control gate, wherein said drain electrode of said first p-mos transistor is connected to said control gate of said first p-mos transitor; a second p-mos transistor having a source electrode connected to said voltage supply, a drain electrode connected to the control gate of said first n-mos transistor, and a control gate connected to the control gate of said first p-mos transistor; a second n-mos transistor having a drain electrode connected to the source electrode of said first p-mos transistor, a control gate connected to a voltage reference, and a source connected to a current sink; and a plurality of n-mos transistors, each having a drain electrode connected to the drain of said second p-mos transistor, a source electrode connected to said current sink, and a control gate connected to one of a plurality of bit lines, wherein each of said plurality of bit lines is connected to a corresponding memory cell.
Claim 6
Dependent Claim
64 words
The EEPROM as recited in claim 3, further including a bit line selection circuit comprising a plurality of inputs including a first input connected to the source electrode of said first n-mos transistor, a plurality of bit line selection inputs, and a plurality of outputs connected to said plurality of bit lines connected to said plurality of n-mos transistors of said voltage regulator circuit.
Claim 7
Independent Claim
143 words
A method of selectively regulating a voltage on each of a plurality of bit lines connected to a plurality of EEPROM cells, comprising the steps of: selecting one of said plurality of bit lines by turning on a selection transistor uniquely corresponding to said selected one of said plurality of bit lines; connecting said selected one of said plurality of bit lines to a voltage source by turning on a control transistor interposed between said selection transistor and said voltage source; detecting a voltage on said selected bit line at a node located between said selection transistor, and an EEPROM cell connected to said selected one of said plurality of bit lines; and comparing said detected voltage against a reference voltage, and adjusting, in response to said comparison, a current flowing through said control transistor until said detected voltage equals said reference voltage.
Claim 8
Independent Claim
143 words
A method of selectively regulating a voltage on each of a plurality of bit lines connected to a plurality of EEPROM cells, comprising the steps of: selecting one of said plurality of bit lines by turning on a selection transistor uniquely corresponding to said selected one of said plurality of bit lines; connecting said selected one of said plurality of bit lines to a voltage source by turning on a control transistor interposed between said selection transistor and said voltage source; detecting a voltage on said selected bit line at a node located between said selection transistor, and an EEPROM cell connected to said selected one of said plurality of bit lines; and comparing said detected voltage against a reference voltage, and adjusting, in response to said comparison, a current flowing through said control transistor until said detected voltage equals said reference voltage.
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