Method for fabricating stacked capacitor of a DRAM cell

Claim 1

A process for fabricating a capacitor of a DRAM cell, comprising the steps of: forming an MOS transistor on a semiconductor substrate, depositing an insulation layer for planarization on the MOS transistor and forming a storage electrode contact hole; then depositing an undoped, first amorphous silicon layer, a doped, second amorphous silicon layer, a doped, third amorphous silicon layer, a doped, fourth amorphous silicon layer and an undoped, fifth amorphous silicon layer; forming a photosensitive film pattern for a storage electrode mask on the fifth amorphous silicon layer; etching the fifth through the first amorphous silicon layers to form a pattern of the fifth through first amorphous silicon layers with the photosensitive film pattern serving as a mask, and then, removing the photosensitive film pattern; annealing the pattern of the first through fifth amorphous silicon layers under a condition, to transform the first through fifth amorphous silicon layers into corresponding first through fifth polysilicon layers with dopants contained in the doped layers being activated and not diffused into the undoped layers; treating the first through fifth polysilicon layers with a selective chemical etchant to form grooves only in the doped second polysilicon layer and the doped fourth polysilicon layer; diffusing dopants in the second and fourth polysilicon layers into the first, third and fifth polysilicon layers by use of a heat treatment, to form a storage electrode; depositing a phosphorous-doped polysilicon film on an entire surface of the storage electrode; and diffusing dopants contained in the polysilicon film into the storage electrode through a heat treatment, to form a bellows storage electrode.