Patent US5519872A successfully refreshed from Google Patents.
US5519872A
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Fast address latch with automatic address incrementing
Assignee: Intel Corp
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Filing: 1993-12-30
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Granted: 1996-05-21
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Expires: 2013-12-30
Abstract
Abstract A latching mechanism captures an address transmitted on a multiplexed address/data bus and preserves it for the full bus cycle. A transparent latch with a multiplexed feedback path allows the address to be quickly captured and decoded. An additional multiplexer and latch cooperate with the first mentioned latch to keep the address stable for a sufficient time to allow latching by slower memory elements. Additional elements are provided to automatically increment the address for multiple data burst operation.
Inventors
- 👤 Narendra Khandekar
- 👤 Dahmane Dahmani
- 👤 Jasmin Ajanovic
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 19:53
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4208; G06F13/4217
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
251 words
An address capture circuit comprising: (a) a first multiplexer having a first input coupled to a communications bus, said bus carrying an address during an address phase, a second input and an output; (b) a first latch having an input coupled to the output of the first multiplexer and an output coupled to the second input of the first multiplexer; (c) a second multiplexer having a first input coupled to the output of the first latch, a second input and an output; (d) a second latch having an input coupled to the output of the second multiplexer and an output providing the address captured by said address capture circuit; (e) an incrementer having an input coupled to the output of the second latch and an output, wherein the output of the incrementer is a digital word having a value equal to a digital word presented at the input of the incrementer incremented by a predetermined quantity; (f) a third multiplexer having a first input coupled to the output of the incrementer, a second input coupled to the output of the second latch and an output; (g) a third latch having an input coupled to the output of the third multiplexer and an output coupled to the second input of the second multiplexer; (h) control means for selecting the second input of the first multiplexer during a bus cycle of the communications bus and for selecting the input of the second and third multiplexer as a function of a bus cycle type.
Claim 2
Dependent Claim
251 words
An address capture circuit comprising: (a) a first multiplexer having a first input coupled to a communications bus, said bus carrying an address during an address phase, a second input and an output; (b) a first latch having an input coupled to the output of the first multiplexer and an output coupled to the second input of the first multiplexer; (c) a second multiplexer having a first input coupled to the output of the first latch, a second input and an output; (d) a second latch having an input coupled to the output of the second multiplexer and an output providing the address captured by said address capture circuit; (e) an incrementer having an input coupled to the output of the second latch and an output, wherein the output of the incrementer is a digital word having a value equal to a digital word presented at the input of the incrementer incremented by a predetermined quantity; (f) a third multiplexer having a first input coupled to the output of the incrementer, a second input coupled to the output of the second latch and an output; (g) a third latch having an input coupled to the output of the third multiplexer and an output coupled to the second input of the second multiplexer; (h) control means for selecting the second input of the first multiplexer during a bus cycle of the communications bus and for selecting the input of the second and third multiplexer as a function of a bus cycle type.
Claim 3
Dependent Claim
13 words
The circuit of claim 1 wherein the control means comprises a state machine.
Claim 4
Dependent Claim
16 words
The circuit of claim 1 wherein the communications bus is a Peripheral Component Interconnect (PCI) bus.
Claim 5
Dependent Claim
26 words
The circuit of claim 1 wherein the control means selects the first input of the third multiplexer when the bus cycle type is a write cycle.
Claim 6
Dependent Claim
26 words
The circuit of claim 1 wherein the control means selects the second input of the third multiplexer when the bus cycle type is a read cycle.
Claim 7
Dependent Claim
294 words
A data processing system comprising: a central processing unit; a first communications bus; a host bridge coupling the central processing unit to the communications bus; a second communications bus; an interbus bridge coupling the first and second communications busses, said interbus bridge including an address capture circuit comprising: (a) a first multiplexer having a first input coupled to a communications bus, said bus carrying an address during an address phase, a second input and an output; (b) a first latch having an input coupled to the output of the first multiplexer and an output coupled to the second input of the first multiplexer; (c) a second multiplexer having a first input coupled to the output of the first latch, a second input and an output; (d) a second latch having an input coupled to the output of the second multiplexer and an output providing the address captured by said address capture circuit; (e) an incrementer having an input coupled to the output of the second latch and an output, wherein the output of the incrementer is a digital word having a value equal to a digital word presented at the input of the incrementer incremented by a predetermined quantity; (f) a third multiplexer having a first input coupled to the output of the incrementer, a second input coupled to the output of the second latch and an output; (g) a third latch having an input coupled to the output of the third multiplexer and an output coupled to the second input of the second multiplexer; (h) control means for selecting the second input of the first multiplexer during a bus cycle of the communications bus and for selecting the input of the second and third multiplexer as a function of a bus cycle type.
Claim 8
Dependent Claim
294 words
A data processing system comprising: a central processing unit; a first communications bus; a host bridge coupling the central processing unit to the communications bus; a second communications bus; an interbus bridge coupling the first and second communications busses, said interbus bridge including an address capture circuit comprising: (a) a first multiplexer having a first input coupled to a communications bus, said bus carrying an address during an address phase, a second input and an output; (b) a first latch having an input coupled to the output of the first multiplexer and an output coupled to the second input of the first multiplexer; (c) a second multiplexer having a first input coupled to the output of the first latch, a second input and an output; (d) a second latch having an input coupled to the output of the second multiplexer and an output providing the address captured by said address capture circuit; (e) an incrementer having an input coupled to the output of the second latch and an output, wherein the output of the incrementer is a digital word having a value equal to a digital word presented at the input of the incrementer incremented by a predetermined quantity; (f) a third multiplexer having a first input coupled to the output of the incrementer, a second input coupled to the output of the second latch and an output; (g) a third latch having an input coupled to the output of the third multiplexer and an output coupled to the second input of the second multiplexer; (h) control means for selecting the second input of the first multiplexer during a bus cycle of the communications bus and for selecting the input of the second and third multiplexer as a function of a bus cycle type.
Claim 9
Dependent Claim
19 words
The data processing system of claim 6 wherein the first communications bus is a Peripheral Component Interconnect (PCI) bus.
Claim 10
Dependent Claim
20 words
The data processing system of claim 6 wherein the second communications bus is an Extended Industry Standard Architecture (EISA) bus.
References Cited (Backward Citations)
US4107786A
Cited
US4112490A
Cited
US4438492A
Cited
US4926312A
Cited
US5157776A
Cited
US5014188A
Cited
US5253348A
Cited
US5235545A
Cited
US5333293A
Cited
US5287481A
Cited
US5375079A
Cited
US5379384A
Cited
US5388133A
Cited
US5450460A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-05-21 | 1999-11-20 | 2000-05-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-05-21 | 2003-11-20 | 2004-05-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-05-21 | 2007-11-20 | 2008-05-21 | $7700.00 | Window Closed / Lapsed |