US5287481A
Expired / Lapsed
US
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Automatic cache flush with readable and writable cache tag memory
Assignee: OPTi Inc
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Filing: 1992-05-04
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Granted: 1994-02-15
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Expires: 2012-05-04
Abstract
Abstract According to the invention, a chipset is provided which powers up in a default state with cacheing disabled and which writes permanently non-cacheable tags into tag RAM entries corresponding to memory addresses being read while cacheing is disabled. Even though no "valid" bit is cleared, erroneous cache hits after cacheing is enabled are automatically prevented since any address which does match a tag in the tag RAM, is a non-cacheable address and will force retrieval directly from main memory anyway. Two cache tag test modes are also described, as is a cache sizing algorithm.
Inventors
- 👤 Fong-Lu Lin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 22:37
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0888; G06F12/0804; G06F12/0891; G06F12/0215
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
147 words
Cache memory control apparatus for use with a cache memory having a plurality of tag data leads, with a memory bus having a plurality of bus address leads and being a first source of tag data and with a second source of tag data different from said memory bus address leads, comprising: a plurality of cache memory control apparatus tag data leads, each coupled to a respective one of said cache memory tag data leads; a plurality of cache memory control apparatus address leads, each coupled to a respective one of a subset of said bus address leads; and a multiplexer having a first input, a second input and an output, said first input being coupled to said control apparatus address leads, said second input being coupled to said second source of tag data and said multiplexer output being coupled to said control apparatus tag data leads.
Claim 2
Dependent Claim
147 words
Cache memory control apparatus for use with a cache memory having a plurality of tag data leads, with a memory bus having a plurality of bus address leads and being a first source of tag data and with a second source of tag data different from said memory bus address leads, comprising: a plurality of cache memory control apparatus tag data leads, each coupled to a respective one of said cache memory tag data leads; a plurality of cache memory control apparatus address leads, each coupled to a respective one of a subset of said bus address leads; and a multiplexer having a first input, a second input and an output, said first input being coupled to said control apparatus address leads, said second input being coupled to said second source of tag data and said multiplexer output being coupled to said control apparatus tag data leads.
Claim 3
Dependent Claim
61 words
Apparatus according to claim 1, for use further with a secondary memory having a predefined non-cacheable address range, wherein said second source comprises a source of a first value which, when written as a tag in said cache memory, associates a corresponding data line in said cache memory with a secondary memory address which is within said predefined non-cacheable address range.
Claim 4
Dependent Claim
20 words
Apparatus according to claim 1, wherein said second source comprises a register bit which is programmable with a desired value.
Claim 5
Dependent Claim
39 words
Apparatus according to claim 2, further comprising a third source of tag data including a register bit which is programmable with a desired value, said multiplexer further having a third input coupled to said third source of tag data.
Claim 6
Dependent Claim
62 words
Apparatus according to claim 1, wherein said memory bus further has a plurality of bus data leads, further comprising: a plurality of cache memory control apparatus data leads, each coupled to a respective one of said bus data leads; and a data path providing information from said cache memory control apparatus tag data leads to said cache memory control apparatus data leads.
Claim 7
Dependent Claim
147 words
Cache memory control apparatus, for use with a cache memory having a plurality of tag data leads and with a memory bus having a plurality of bus data leads and a plurality of bus address leads, comprising: a plurality of first data leads coupled to respective ones of said bus data leads; a plurality of second data leads coupled to respective ones of said tag data leads; a plurality of first address leads coupled to respective ones of a subset of said bus address leads; a first data path providing information from said first address leads to said second data leads; and a second data path providing information from said second data leads to said first data leads wherein said second data path further comprises: a register readable via said first data leads; and means for writing said information from said second data leads into said register.
Claim 8
Dependent Claim
147 words
Cache memory control apparatus, for use with a cache memory having a plurality of tag data leads and with a memory bus having a plurality of bus data leads and a plurality of bus address leads, comprising: a plurality of first data leads coupled to respective ones of said bus data leads; a plurality of second data leads coupled to respective ones of said tag data leads; a plurality of first address leads coupled to respective ones of a subset of said bus address leads; a first data path providing information from said first address leads to said second data leads; and a second data path providing information from said second data leads to said first data leads wherein said second data path further comprises: a register readable via said first data leads; and means for writing said information from said second data leads into said register.
Claim 9
Dependent Claim
32 words
Apparatus according to claim 6, wherein said register is further writable via said first data leads, further comprising a third data path providing information from said register to said second data leads.
Claim 10
Dependent Claim
68 words
Apparatus according to claim 7 for use further with a secondary memory having a predefined non-cacheable address range, further comprising a fourth data path for providing to said second data leads a first value which, when written as a tag in said cache memory, associates a corresponding data line in said cache memory with an address in said secondary memory which is within said predefined non-cacheable address range.
References Cited (Backward Citations)
US4493026A
Cited
US5091846A
Cited
US4831581A
Cited
US4831520A
Cited
US5091845A
Cited
US5157774A
Cited
US5095428A
Cited
US5097532A
Cited
US5119485A
Cited
US5182802A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-02-14 | 1997-08-16 | 1998-02-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-02-14 | 2001-08-16 | 2002-02-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-02-14 | 2005-08-16 | 2006-02-15 | $7700.00 | Window Closed / Lapsed |