High speed memory for microcomputer systems

Claim 2

In a computer system having a CPU, a main memory system and a data bus interconnecting said CPU and said main memory system, said main memory system comprising: memory device means for storing information and having a first data port for providing random access to memory cells within said memory device means and a second data port coupled to a shift register within said memory device means, said shift register for being loaded with the contents of a row of said memory cells and further being able to sequentially expose each element of its contents at said second data port; multiplexer means for selecting either one of said data ports and for connecting said selected port to said data bus for providing said CPU with access to information stored in said memory device via said selected port; and controller means coupled to said memory device means for controlling said shift register and said multiplexer means.

Claim 3

In a computer having a CPU and a data bus, a main memory system, as recited in claim 1, wherein said controller means comprises: latch means for containing the address of a first, executed instruction word; incrementor means for receiving the contents of said latch means and developing an address value which corresponds to a second instruction word physically located upwardly adjacent to said first, executed instruction word; comparator means for evaluating a coincidence of said developed address value with the address of a requested instruction word; and means responsive to said comparator means for modifying the contents of said shift register.

Claim 4

In a computer system, having a CPU and a data bus, a main memory system, as recited in claim 1, wherein said memory device means comprises a plurality of dual-port random access memory devices.

Claim 5

In a computer system, having a CPU and a data bus, a main memory system, as recited in claim 1, wherein said memory device means comprises a plurality of video random access memory devices.

Claim 6

In a computer system having a CPU, a main memory system and a data bus interconnecting said CPU and said main memory system, said main memory system comprising: memory device means for storing information and having a first data port for providing random access to memory and a second data port coupled to a shift register within said memory device means, said shift register for being loaded with the contents of a row of said memory cells and for shifting its contents so as to sequentially expose each element of its contents at said second data port; multiplexer means for selecting either one of said data ports and for connecting said selected port to said data bus for providing said CPU with access to information stored in said memory device via said selected port; latch means for containing the address of a first instruction word; incrementor means for receiving the contents of said latch means and developing an address value which corresponds to a second instruction word; comparator means for evaluating a coincidence of said developed address value with the address of a presently requested instruction word; and means responsive to said comparator means for modifying the contents of said shift register.

Claim 7

In a computer system having a CPU, a main memory system and a data bus interconnecting said CPU and said main memory system, said main memory system comprising: memory device means for storing information and having a first data port for providing random access to memory and a second data port coupled to a shift register within said memory device means, said shift register for being loaded with the contents of a row of said memory cells and for shifting its contents so as to sequentially expose each element of its contents at said second data port; multiplexer means for selecting either one of said data ports and for connecting said selected port to said data bus for providing said CPU with access to information stored in said memory device via said selected port; latch means for containing the address of a first instruction word; incrementor means for receiving the contents of said latch means and developing an address value which corresponds to a second instruction word; comparator means for evaluating a coincidence of said developed address value with the address of a presently requested instruction word; and means responsive to said comparator means for modifying the contents of said shift register.

Claim 14

A method for transferring a requested instruction word from a main memory to a CPU, as recited in claim 8, wherein said modifying step, responsive to the outcome of said comparing step, comprises: shifting the contents of said shift register to expose at said serial port said requested instruction word, in the presence of said coincidence; and loading said shift register with the contents of a row of memory words containing said requested instruction word, and shifting the contents of said shift register to expose at said serial port said requested instruction word, in the absence of said coincidence.

Claim 15

A method for transferring a requested instruction word from a main memory to a CPU, as recited in claim 8, wherein said modifying step in the presence of said coincidence comprises shifting the contents of said shift register to expose at said serial port said requested instruction word.

Claim 16

A method for transferring a requested instruction word from a main memory to a CPU, as recited in claim 8, wherein said modifying step in the absence of said coincidence comprises loading said shift register with the contents of a row of memory words containing said requested instruction word, and shifting the contents of said shift register to expose at said serial port said requested instruction word.

Claim 17

A main memory system for temporarily storing instructions and data in a computer system having a data bus interconnecting a CPU and said main memory system, said main memory system comprising: a plurality of integrated circuit memory devices, each of said devices having a parallel data port for providing random access to memory cells therein and a serial data port coupled to a shift register therein, said shift register for being located with the contents of a row of memory cells and to shift its contents to sequentially expose each element of its contents at said serial data port; means for selecting either one of said data ports and for coupling said selected data port to said data bus for providing said CPU with access to stored information via said selected data port; and means coupled to said devices and said means for selecting for controlling said shift register and said means for selecting.

Claim 18

A main memory system for temporarily storing instructions and data in a computer system having a data bus interconnecting a CPU and said main memory system, said main memory system comprising: a plurality of integrated circuit memory devices, each of said devices having a parallel data port for providing random access to memory cells therein and a serial data port coupled to a shift register therein, said shift register for being located with the contents of a row of memory cells and to shift its contents to sequentially expose each element of its contents at said serial data port; means for selecting either one of said data ports and for coupling said selected data port to said data bus for providing said CPU with access to stored information via said selected data port; and means coupled to said devices and said means for selecting for controlling said shift register and said means for selecting.

Claim 19

A main memory system for temporarily storing instructions and data for processing in a computer system having a data bus interconnecting a CPU and said main memory system, said main memory system comprising: a plurality of video random access memory integrated circuit devices arranged in a main memory array configuration, each of said devices having a parallel data port for providing random access to memory cells therein and a serial data port coupled to a shift register therein, said shift register for being loaded with the contents of a row of memory cells and to shift its contents to sequentially expose each element of its contents at said serial data port; means for selecting either one of said data ports and for coupling said selected data port to said data bus for providing said CPU with access to stored information via said selected data port; latch means for containing the address of a first, executed instruction word; incrementor means for receiving the contents of said latch means and for developing an address value which corresponds to a second instruction word physically located upwardly adjacent to said first, executed instruction word; comparator means for evaluating a coincidence of said developed address value with the address of a requested instruction word; and means responsive to said comparator means for modifying the contents of said shift register.

Claim 20

A main memory system for temporarily storing instructions and data for processing in a computer system having a data bus interconnecting a CPU and said main memory system, said main memory system comprising: a plurality of video random access memory integrated circuit devices arranged in a main memory array configuration, each of said devices having a parallel data port for providing random access to memory cells therein and a serial data port coupled to a shift register therein, said shift register for being loaded with the contents of a row of memory cells and to shift its contents to sequentially expose each element of its contents at said serial data port; means for selecting either one of said data ports and for coupling said selected data port to said data bus for providing said CPU with access to stored information via said selected data port; latch means for containing the address of a first, executed instruction word; incrementor means for receiving the contents of said latch means and for developing an address value which corresponds to a second instruction word physically located upwardly adjacent to said first, executed instruction word; comparator means for evaluating a coincidence of said developed address value with the address of a requested instruction word; and means responsive to said comparator means for modifying the contents of said shift register.

Claim 21

A main memory system for use in a computer system having a central processing unit for manipulating instructions and data temporarily stored in said main memory system, said main memory system having an associated, integral cache for expediting the retrieval of instructions from said main memory system, said main memory system comprising: a plurality of integrated circuit memory devices, each of said devices having a parallel data port for providing random access to memory cells therein and a serial data port coupled to a shift register therein, said shift register for being loaded with the contents of a row of memory cells and to shift its contents to sequentially expose each element of its contents at said serial data port; means for selecting either one of said data ports and for coupling said selected data port to a data bus coupled to said central processing unit to provide said central processing unit with access to stored information via said selected data port; and means for controlling said shift register and said means for selecting.

Claim 22

A main memory system for use in a computer system having a central processing unit for manipulating instructions and data temporarily stored in said main memory system, said main memory system having an associated, integral cache for expediting the retrieval of instructions from said main memory system, said main memory system comprising: a plurality of integrated circuit memory devices, each of said devices having a parallel data port for providing random access to memory cells therein and a serial data port coupled to a shift register therein, said shift register for being loaded with the contents of a row of memory cells and to shift its contents to sequentially expose each element of its contents at said serial data port; means for selecting either one of said data ports and for coupling said selected data port to a data bus coupled to said central processing unit to provide said central processing unit with access to stored information via said selected data port; and means for controlling said shift register and said means for selecting.