Video system with XY addressing capabilities

Claim 2

A video system comprising: a data processor means for manipulating data including pixel image data forming a video image in accordance with program instructions, said data processor means having a control bus for transmitting control signals including an XY memory access signal, a data bus and a first address bus; a memory means connected to said data bus and having a second address bus, for storing and recalling data, including pixel image data corresponding to a visual image, in memory locations corresponding to addresses received from said second address bus; a video system controller means connected to said data bus, said first address bus and said second address bus for controlling the transfer of data between said data processor means and said memory means by control of the address applied to said memory means via said second address bus, said video system controller means including an XY address register means connected to said data bus for storing the row and column addresses corresponding to a particular display location expressed as an X raster position code and a Y raster position code, an XY offset register means connected to said XY address register means having data stored therein defining the number of bits of said XY address register means defining said X raster position code and the number of bits of said XY address register means defining said Y raster position code, and an addressing means connected to said control bus, said first address bus, said second address bus and said XY address register means for performing an XY memory access by providing an address from said XY address register means to said memory means via said second address bus upon receipt of an XY memory access signal; and a display means connected to said memory means for generating an operator perceivable visual display corresponding to said video data stored in said memory means.

Claim 3

A video system as claimed in claim 1, wherein: said data processing means further includes means for transmitting an XY address update control signal on said control bus; and said video system controller means further includes an XY update means connected to said control bus and said XY address register means for separately updating said X raster position code and said Y raster position code stored in said XY address register means in accordance with said XY address update control signal after each XY memory access.

Claim 4

A video system as claimed in claim 2, wherein: said XY address update control signal transmitted by said data processor means includes an increment X update control signal; and said XY update means increments the X raster position code stored in said XY address register means after an XY memory access upon receipt of an increment X signal update control signal.

Claim 5

A video system as claimed in claim 2, wherein: said XY address update control signal transmitted by said data processor means includes a decrement X update control signal; and said XY update means decrements the X raster position code stored in said XY address register means after an XY memory access upon receipt of a decrement X signal update control signal.

Claim 6

A video system as claimed in claim 2, wherein: said XY address update control signal transmitted by said data processor means includes a clear X update control signal; and said XY update means clears the X raster position code stored in said XY address register means after an XY memory access upon receipt of a clear X signal update control signal.

Claim 7

A video system as claimed in claim 2, wherein: said XY address update control signal transmitted by said data processor means includes an increment Y update control signal; and said XY update means increments the Y raster position code stored in said XY address register means after an XY memory access upon receipt of an increment Y signal update control signal.

Claim 8

A video system as claimed in claim 2, wherein: said XY address update control signal transmitted by said data processor means includes a decrement Y update control signal; and said XY update means decrements the Y raster position code stored in said XY address register means after an XY memory access upon receipt of a decrement Y signal update control signal.

Claim 9

A video system as claimed in claim 2, wherein: said XY address update control signal transmitted by said data processor means includes a clear Y update control signal; and said XY update means clears the Y raster position code stored in said XY address register means after an XY memory access upon receipt of a clear Y signal update control signal.

Claim 10

A video system as claimed in claim 2, wherein: said XY address update control signal transmitted by said data processor means includes an increment X increment Y update control signal; and said XY update means increments the X raster position code stored in said XY address register means and increments the Y raster position stored in said XY address register means after an XY memory access upon receipt of an increment X increment Y signal update control signal.

Claim 11

A video system as claimed in claim 2, wherein: said XY address update control signal transmitted by said data processor means includes an increment X decrement Y update control signal; and said XY update means increments the X raster position code stored in said XY address register means and decrements the Y raster position stored in said XY address register means after an XY memory access upon receipt of an increment X decrement Y signal update control signal.

Claim 12

A video system as claimed in claim 2, wherein: said XY address update control signal transmitted by said data processor means includes an increment X clear Y update control signal; and said XY update means increments the X raster position code stored in said XY address register means and clears the Y raster position stored in said XY address register means after an XY memory access upon receipt of an increment X clear Y signal update control signal.

Claim 13

A video system as claimed in claim 2, wherein: said XY address update control signal transmitted by said data processor means includes a decrement X increment Y update control signal; and said XY update means decrements the X raster position code stored in said XY address register means and increments the Y raster position stored in said XY address register means after an XY memory access upon receipt of a decrement X increment Y signal update control signal.

Claim 14

A video system as claimed in claim 2, wherein: said XY address update control signal transmitted by said data processor means includes a decrement X decrement Y update control signal; and said XY update means decrements the X raster position code stored in said XY address register means and decrements the Y raster position stored in said XY address register means after an XY memory access upon receipt of an decrement X decrement Y signal update control signal.

Claim 15

A video system as claimed in claim 2, wherein: said XY address update control signal transmitted by said data processor means includes an decrement X clear Y update control signal; and said XY update means decrements the X raster position code stored in said XY address register means and clears the Y raster position stored in said XY address register means after an XY memory access upon receipt of a decrement X clear Y signal update control signal.

Claim 16

A video system as claimed in claim 2, wherein: said XY address update control signal transmitted by said data processor means includes a clear X increment Y update control signal; and said XY update means clears the X raster position code stored in said XY address register means and increments the Y raster position stored in said XY address register means after an XY memory access upon receipt of a clear X increment Y signal update control signal.

Claim 17

A video system as claimed in claim 2, wherein: said XY address update control signal transmitted by said data processor means includes a clear X decrement Y update control signal; and said XY update means clears the X raster position code stored in said XY address register means and decrements the Y raster position stored in said XY address register means after an XY memory access upon receipt of a clear X decrement Y signal update control signal.

Claim 18

A video system as claimed in claim 2, wherein: said XY address update contol signal transmitted by said data processor means includes a clear X clear Y update control signal; and said XY update means clears the X raster position code stored in said XY address register means and clears the Y raster position stored in said XY address register means after an XY memory access upon receipt of a clear X clear Y signal update control signal.

Claim 19

A video system as claimed in claim 2, wherein: said XY offset register means is further connected to said data bus whereby said data processor means can alter the data stored therein thereby redefining the number of bits of said XY address register means defining said X raster position code and the number of bits of said XY address register means defining said Y raster position code.

Claim 20

A video system as claimed in claim 2, wherein: said XY offset register means is further connected to said data bus and further includes a plurality of offset bits, whereby said data processor means can alter said offset bits stored in said XY offset register means; and said addressing means provides an address from said XY address register means to said memory means via said second address bus upon receipt of an XY memory access signal by concatenation of said X raster position code, said Y raster position code and said plurality of offset bits stored in said XY offset register means.

Claim 21

A video system as claimed in claim 2, wherein: said memory means has a plurality of memory planes, each memory plane having a separate memory write enable input, whereby pixel image data having said predetermined plural number of bits is stored at each memory location; said XY offset register means is further connected to said data bus and further includes a plurality of plane select bits, whereby said data processor means can alter said plane select bits stored in said XY offset register means; and said addressing means provides an address from said XY address register means to said memory means and further provides a selection of memory planes of said memory means in accordance with said plane select bits stored in said XY offset register means.

Claim 22

A video system comprising: a data processor means for manipulating data including pixel image data forming a video image in accordance with program instructions, said data processor means having a control bus for transmitting control signals, said control signals including a direct memory access control signal, an XY indirect memory access control signal and an XY address update control signal, a data bus and a first address bus; a memory means connected to said data bus and having a second address bus, for storing and recalling data, including pixel image data corresponding to a visual image, in memory locations corresponding to addresses received from said second address bus, said memory means constructed to receive separately a row address and a column address time multiplexed on said second address bus; a video system controller means connected to said data bus, said first address bus and said second address bus for controlling the transfer of data between said data processor means and said memory means by control of the address applied to said memory means via said second address bus, said video system controller further including a row address latch connected to said first address bus for storing a row address received from said data processor means, a column address latch connected to said first address bus for storing a column address received from said data processor means, an XY address register means connected to said data bus for storing the row and column addresses corresponding to a particular display location expressed as an X raster position code and a Y raster position code received from said data processor means, the most significant bits being said Y raster position code and the least significant bits being said X raster position code, an XY offset register means connected to said control bus and said XY address register means having data stored therein defining the number of bits of said XY address register means defining said X raster position code and the number of bits of said XY address register means defining said Y raster position code, said XY offset register means being alterable by said data processor means, a multiplexer means connected to said control bus, said second address bus and said row address latch, said column address latch and said XY address register means for sequentially applying said row address stored in said row address latch and then applying said column address stored in said column address latch to said second address bus in response to a direct memory access control signal, and for sequentially supplying said row address stored in said XY address latch and then said column address stored in said XY address latch to said second address bus in response to an XY indirect memory access control signal, and an XY update means connected to said control bus and said XY address register means for separately updating said X raster position code and said Y raster position code stored in said XY address register means in accordance with said XY address update control signal after each XY memory access; and a display means connected to said memory means for generating an operator perceivable visual display corresponding to said video data stored in said memory means.

Claim 23

A video system comprising: a data processor means for manipulating data including pixel image data forming a video image in accordance with program instructions, said data processor means having a control bus for transmitting control signals, said control signals including a direct memory access control signal, an XY indirect memory access control signal and an XY address update control signal, a data bus and a first address bus; a memory means connected to said data bus and having a second address bus, for storing and recalling data, including pixel image data corresponding to a visual image, in memory locations corresponding to addresses received from said second address bus, said memory means constructed to receive separately a row address and a column address time multiplexed on said second address bus; a video system controller means connected to said data bus, said first address bus and said second address bus for controlling the transfer of data between said data processor means and said memory means by control of the address applied to said memory means via said second address bus, said video system controller further including a row address latch connected to said first address bus for storing a row address received from said data processor means, a column address latch connected to said first address bus for storing a column address received from said data processor means, an XY address register means connected to said data bus for storing the row and column addresses corresponding to a particular display location expressed as an X raster position code and a Y raster position code received from said data processor means, the most significant bits being said Y raster position code and the least significant bits being said X raster position code, an XY offset register means connected to said control bus and said XY address register means having data stored therein defining the number of bits of said XY address register means defining said X raster position code and the number of bits of said XY address register means defining said Y raster position code, said XY offset register means being alterable by said data processor means, a multiplexer means connected to said control bus, said second address bus and said row address latch, said column address latch and said XY address register means for sequentially applying said row address stored in said row address latch and then applying said column address stored in said column address latch to said second address bus in response to a direct memory access control signal, and for sequentially supplying said row address stored in said XY address latch and then said column address stored in said XY address latch to said second address bus in response to an XY indirect memory access control signal, and an XY update means connected to said control bus and said XY address register means for separately updating said X raster position code and said Y raster position code stored in said XY address register means in accordance with said XY address update control signal after each XY memory access; and a display means connected to said memory means for generating an operator perceivable visual display corresponding to said video data stored in said memory means.

Claim 24

A video system as claimed in claim 21, wherein: said control bus includes an XY address update control signal of 4 bits for specifying the type of update of the X raster position code and the Y raster position code upon an XY indirect memory access control signal; and said XY update means does not alter said X raster position code or said Y raster position code in response to an XY address update control signal in a first state; increments said X raster position code in response to an XY address update control signal in a second state; decrements said X raster position code in response to an XY address update control signal in a third state; clears said X raster position code in response to an XY address update control signal in a fourth state; increments said Y raster position code in response to an XY address update control signal in a fifth state; increments said X raster position code and increments said Y raster position code in response to an XY address update control signal in a sixth state; decrements said X raster position code and increments said Y raster position code in response to an XY address update control signal in a seventh state; clears said X raster position code and increments said Y raster position code in response to an XY address update control signal in an eighth state; decrements said Y raster position code in response to an XY address update control signal in an ninth state; increments said X raster position code and decrements said Y raster code in response to an XY address update control signal in a tenth state; decrements said X raster position code and decrements said Y raster position code in response to an XY address update control signal in an eleventh state; clears said X raster position code and decrements said Y raster position code in response to an XY address update control signal in an twelfth state; clears said Y raster position code in response to an XY address update control signal in a thirteenth state; increments said X raster position code and clears said Y raster position code in response to an XY address update control signal in a fourteenth state; decrements said X raster position code and clears said Y raster position code in response to an XY address update control signal in a fifteenth state; and clears said X raster position code and clears said Y raster position code in response to an XY address update control signal in a sixteenth state.

Claim 25

A video system as claimed in claim 21, wherein: said XY offset register means is further connected to said data bus and further includes a first and second offset bits, whereby said data processor means can alter said offset bits stored in said XY offset register means; and said multiplexer means provides said row address to said memory means via said second address bus upon receipt of an XY memory access signal by providing said first offset bit as the most significant bit of said row address and recalling the least significant bits from said XY address register means and provides said column address to said memory means via said second address bus upon receipt of an XY memory access signal by providing said second offset bit as the most significant bit of said column address and recalling the least significant bits from said XY address register means.

Claim 26

A video system as claimed in claim 21, wherein: said memory means has a plurality of memory planes, each memory plane having a separate memory write enable input, whereby pixel image data having said predetermined plural number of bits is stored at each memory location; said XY offset register means is further connected to said data bus and further includes a plurality of plane select bits, whereby said data processor means can alter said plane select bits stored in said XY offset register means; and said multiplexer means provides an address from said XY address register means to said memory means and further provides a selection of memory planes of said memory means in accordance with said plane select bits stored in said XY offset register means.

Claim 29

A method as claimed in claim 25, further including: incrementing, decrementing, clearing or not altering said X raster position code and said Y raster position code in response to said XY address update control signal.

Claim 30

A method as claimed in claim 25, further including: altering via the data processor the stored data defining the number of bits of said stored XY address register means defining said X raster position code and the number of bits of said stored XY address register means defining said Y raster position code.

Claim 31

A method as claimed in claim 25, further including: storing first and second offset bits alterable by the data processor; and said step of sequentially supplying a row address and then a column address from said stored XY address to the memory in response to an XY indirect memory access control signal includes providing said first offset bit as the most significant bit of said row address and recalling the least significant bits of said row address from said stored XY address register means and providing said second offset bit as the most significant bit of said column address and recalling the least significant bits from said stored XY address.

Claim 32

A method as claimed in claim 25, wherein: storing a plurality of plane select bits alterable by the data processor; and selecting memory planes of the memory in accordance with said stored plane select bits.