Synchronization of CRT controller chips

Claim 1

In a system having a source of clock signals, a processor generating commands, an input/output device, and a first and second independently actuable controller for applying a counterpart first and second non-overlapping functionally distinct set of control signals to said device, each controller generating its counterpart set of control signals periodically conditioned by a processor command and in response to a predetermined number of clocking signals, wherein the improvement comprises means for synchronizing the controllers including: gating means reponsive to processor command for applying clock signals selectively to said first and second controllers; means for applying a subset of control signals from the first controller to the second controller as a timing reference; and means responsive to the generation of the first and second set of control signals for selectively enabling or disabling the application of clocking signals to the controllers so as to enforce coincident generation of said first and second set of control signals.