US5519654A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device with external capacitor to charge pump in an EEPROM circuit
Assignee: Toshiba Corp
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Filing: 1995-05-25
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Granted: 1996-05-21
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Expires: 2015-05-25
Abstract
Abstract A semiconductor memory device having a memory cell array with a plurality of transistors (memory cells MC) disposed in a matrix form capable of electrically altering data. In writing data to a plurality of memory cells (MC), a write voltage (V pp ') is applied to the plurality of memory cells (MC) from a plurality of write circuits (7). The write voltage is generated by boosting an internal voltage (V CC ) by a charge pump circuit (21). In writing data, one of the following methods is used. The plurality of write circuits (7) are sequentially activated by a write control circuit (20) at intervals of delayed timings. The operating point of each memory cell (transistor)(MC) is controlled by operating point control means so as to reduce a current. A capacitor is connected to the output side of the charge pump circuit, and a boosted write voltage is supplied via the capacitor to the write circuit.
Inventors
- 👤 Hideo Kato
- 👤 Masamichi Asano
- 👤 Shinji Saito
- 👤 Shigeru Matsuda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 17:14
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/30; G11C16/10; G11C16/12
Claims Analysis
Total Claims: 51
Claim 1
Independent Claim
229 words
A semiconductor memory device having a memory cell array which includes a plurality of memory cells arranged into a matrix pattern on a main chip, data being written in, read from, and erased from at least one selected memory cell formed of a transistor, data respectively being written in and erased from the at least one memory cell on the basis of a write voltage and an erase voltage obtained by boosting an internal supply voltage, the semiconductor memory device comprising: a plurality of write circuits each for applying a write voltage to the at least one selected memory cell to write data therein; an erase circuit for applying an erase voltage to the at least one selected memory cell to erase data therefrom; a boost circuit for boosting the internal supply voltage to generate the write voltage and the erase voltage and outputting the generated write and erase voltage through a boosted voltage output terminal; an on-chip pad terminal for outputting an output of said boost circuit; an outer terminal electrically connected to the on-chip pad terminal, and configured to connect an external circuit element thereto; and a capacitor externally connected to said outer terminal, and configured to receive an electric charge from said boost circuit, data being written in and erased from the at least one selected memory cell by discharging the electric charge of said capacitor.
Claim 2
Dependent Claim
229 words
A semiconductor memory device having a memory cell array which includes a plurality of memory cells arranged into a matrix pattern on a main chip, data being written in, read from, and erased from at least one selected memory cell formed of a transistor, data respectively being written in and erased from the at least one memory cell on the basis of a write voltage and an erase voltage obtained by boosting an internal supply voltage, the semiconductor memory device comprising: a plurality of write circuits each for applying a write voltage to the at least one selected memory cell to write data therein; an erase circuit for applying an erase voltage to the at least one selected memory cell to erase data therefrom; a boost circuit for boosting the internal supply voltage to generate the write voltage and the erase voltage and outputting the generated write and erase voltage through a boosted voltage output terminal; an on-chip pad terminal for outputting an output of said boost circuit; an outer terminal electrically connected to the on-chip pad terminal, and configured to connect an external circuit element thereto; and a capacitor externally connected to said outer terminal, and configured to receive an electric charge from said boost circuit, data being written in and erased from the at least one selected memory cell by discharging the electric charge of said capacitor.
Claim 3
Dependent Claim
29 words
The semiconductor memory device of claim 1, wherein said external terminal is an external lead terminal projecting from a package, and said capacitor being connected externally to the package.
Claim 4
Dependent Claim
37 words
The semiconductor memory device of claim 1, wherein said capacitor is formed on or in a capacitor chip different from the main chip, the capacitor chip and the main chip being both assembled together within the package.
Claim 5
Dependent Claim
31 words
The semiconductor memory device of claim 3, wherein said on-chip pad terminal formed on the main chip is connected to said capacitor formed on the capacitor chip through a bonding wire.
Claim 6
Dependent Claim
27 words
The semiconductor memory device of claim 3, wherein said capacitor is formed by stacking a plurality of insulating films and a plurality of poly silicon layers alternately.
Claim 7
Dependent Claim
26 words
The semiconductor memory device of claim 3, wherein said capacitor includes a plurality of trenches formed in a semiconductor substrate and filled with an insulating substance.
Claim 8
Dependent Claim
62 words
The semiconductor memory device of claim 1, further comprising a write-enable and erase-enable status discriminate circuit for discriminating whether data can be written in or erased from the at least one selected memory cell and outputting a discriminate signal indicative thereof, data being written in or erased from the at least one selected memory cell on the basis of the discriminate signal.
Claim 9
Dependent Claim
62 words
The semiconductor memory device of claim 2, further comprising a write-enable and erase-enable status discriminate circuit for discriminating whether data can be written in or erased from the at least one selected memory cell and outputting a discriminate signal indicative thereof, data being written in or erased from the at least one selected memory cell on the basis of the discriminate signal.
Claim 10
Dependent Claim
62 words
The semiconductor memory device of claim 3, further comprising a write-enable and erase-enable status discriminate circuit for discriminating whether data can be written in or erased from the at least one selected memory cell and outputting a discriminate signal indicative thereof, data being written in or erased from the at least one selected memory cell on the basis of the discriminate signal.
Claim 11
Dependent Claim
60 words
The semiconductor memory device of claim 1, further comprising: a write timer responsive to a write start signal, for setting the semiconductor memory device to a write operation status for a first constant time; and an erase timer responsive to an erase start signal, for setting the semiconductor memory device to an erase operation status for a second constant time.
Claim 12
Dependent Claim
58 words
The semiconductor memory device of claim 2, further comprising: a write timer responsive to a write start signal, for setting the semiconductor device to a write operation status for a first constant time; and an erase timer responsive to an erase start signal, for setting the semiconductor device to an erase operation status for a second constant time.
Claim 13
Dependent Claim
58 words
The semiconductor memory device of claim 3, further comprising: a write timer responsive to a write start signal, for setting the semiconductor device to a write operation status for a first constant time; and an erase timer responsive to an erase start signal, for setting the semiconductor device to an erase operation status for a second constant time.
Claim 14
Dependent Claim
77 words
The semiconductor memory device of claim 1, wherein: the memory cell array has a plurality of memory cell units each including a plurality of memory cells; each of said write circuits is provided for a corresponding one of said memory cell units; and wherein said semiconductor memory device further comprises a write control circuit for activating one of said write circuits in sequence, to enable a write operation through said boost circuit having a small driving capability.
Claim 15
Dependent Claim
77 words
The semiconductor memory device of claim 2, wherein: the memory cell array has a plurality of memory cell units each including a plurality of memory cells; each of said write circuits is provided for a corresponding one of said memory cell units; and wherein said semiconductor memory device further comprises a write control circuit for activating one of said write circuits in sequence, to enable a write operation through said boost circuit having a small driving capability.
Claim 16
Dependent Claim
77 words
The semiconductor memory device of claim 3, wherein: the memory cell array has a plurality of memory cell units each including a plurality of memory cells; each of said write circuits is provided for a corresponding one of said memory cell units; and wherein said semiconductor memory device further comprises a write control circuit for activating one of said write circuits in sequence, to enable a write operation through said boost circuit having a small driving capability.
Claim 17
Dependent Claim
45 words
The semiconductor memory device of claim 1, further comprising operating point control means for setting an operating point of the respective transistor in each of said memory cells so as to minimize write current flowing therethrough in a writing operation, for reduction of current consumption.
Claim 18
Dependent Claim
44 words
The semiconductor memory device of claim 2, further comprising operating point control means for setting an operating point of the respective transistor in each of said memory cells so to minimize write current flowing therethrough in a writing operation, for reduction of current consumption.
Claim 19
Dependent Claim
45 words
The semiconductor memory device of claim 3, further comprising operating point control means for setting an operating point of the respective transistor in each of said memory cells so as to minimize write current flowing therethrough in a writing operation, for reduction of current consumption.
Claim 20
Dependent Claim
197 words
A semiconductor memory device having a memory cell array which includes a plurality of memory cells arranged into a matrix pattern on a main chip, data being written in, read from, and erased from at least one selected memory cell formed of a transistor, data being respectively written in and erased from the at least one memory cell on the basis of a write voltage and an erase voltage obtained by boosting an internal supply voltage, said semiconductor memory device comprising: a plurality of write circuits each for applying a write voltage to a selected memory cell to write data therein; a boost circuit for boosting the internal supply voltage to generate the write voltage and outputting the generated write voltage through a boosted voltage output terminal; an on-chip pad terminal for outputting an output of said boost circuit; an outer terminal electrically connected to the on-chip pad terminal and configured to connect an external circuit element thereto; and a capacitor externally connected to said outer terminal and configured to receive an electric charge from said boost circuit, data being written in the at least one selected memory cell by discharging the electric charge of said capacitor.
Claim 21
Dependent Claim
197 words
A semiconductor memory device having a memory cell array which includes a plurality of memory cells arranged into a matrix pattern on a main chip, data being written in, read from, and erased from at least one selected memory cell formed of a transistor, data being respectively written in and erased from the at least one memory cell on the basis of a write voltage and an erase voltage obtained by boosting an internal supply voltage, said semiconductor memory device comprising: a plurality of write circuits each for applying a write voltage to a selected memory cell to write data therein; a boost circuit for boosting the internal supply voltage to generate the write voltage and outputting the generated write voltage through a boosted voltage output terminal; an on-chip pad terminal for outputting an output of said boost circuit; an outer terminal electrically connected to the on-chip pad terminal and configured to connect an external circuit element thereto; and a capacitor externally connected to said outer terminal and configured to receive an electric charge from said boost circuit, data being written in the at least one selected memory cell by discharging the electric charge of said capacitor.
Claim 22
Dependent Claim
29 words
The semiconductor memory device of claim 19, wherein said external terminal is an external lead terminal projecting from a package, and said capacitor being connected externally to the package.
Claim 23
Dependent Claim
37 words
The semiconductor memory device of claim 19, wherein said capacitor is formed on or in a capacitor chip different from the main chip, the capacitor chip and the main chip being both assembled together within the package.
Claim 24
Dependent Claim
31 words
The semiconductor memory device of claim 21, wherein said on-chip pad terminal formed on the main chip is connected to said capacitor formed on the capacitor chip through a bonding wire.
Claim 25
Dependent Claim
27 words
The semiconductor memory device of claim 21, wherein said capacitor is formed by stacking a plurality of insulating films and a plurality of poly silicon layers alternately.
Claim 26
Dependent Claim
26 words
The semiconductor memory device of claim 21, wherein said capacitor includes a plurality of trenches formed in a semiconductor substrate and filled with an insulating substance.
Claim 27
Dependent Claim
46 words
The semiconductor memory device of claim 19, further comprising a write-enable status discriminate circuit for discriminating whether data can be written in each memory cell and outputting a discriminate signal indicative thereof, data being written in each memory cell on the basis of the discriminate signal.
Claim 28
Dependent Claim
46 words
The semiconductor memory device of claim 20, further comprising a write-enable status discriminate circuit for discriminating whether data can be written in each memory cell and outputting a discriminate signal indicative thereof, data being written in each memory cell on the basis of the discriminate signal.
Claim 29
Dependent Claim
45 words
The semiconductor memory device of claim 21, further comprising a write-enable status discriminate circuit for discriminating whether data can be written each memory cell and outputting a discriminate signal indicative thereof, data being written in each memory cell on the basis of the discriminate signal.
Claim 30
Dependent Claim
33 words
The semiconductor memory device of claim 19, further comprising a write timer responsive to a write start signal, for setting the semiconductor memory device to a write operation status for a constant time.
Claim 31
Dependent Claim
33 words
The semiconductor memory device of claim 20, further comprising a write timer responsive to a write start signal, for setting the semiconductor memory device to a write operation status for a constant time.
Claim 32
Dependent Claim
33 words
The semiconductor memory device of claim 21, further comprising a write timer responsive to a write start signal, for setting the semiconductor memory device to a write operation status for a constant time.
Claim 33
Dependent Claim
76 words
The semiconductor memory device of claim 19, wherein: the memory cell array includes a plurality of memory cell units each composed of a plurality of memory cells; each of said write circuits is provided for a corresponding one of said memory cell units; and said write circuits further comprise a write control circuit for activating one of said write circuits in sequence, to enable a write operation through said boost circuit having a small driving capability.
Claim 34
Dependent Claim
76 words
The semiconductor memory device of claim 20, wherein: the memory cell array includes a plurality of memory cell units each composed of a plurality of memory cells; each of said write circuits is provided for a corresponding one of said memory cell units; and said write circuits further comprise a write control circuit for activating one of said write circuits in sequence, to enable a write operation through said boost circuit having a small driving capability.
Claim 35
Dependent Claim
76 words
The semiconductor memory device of claim 21, wherein: the memory cell array includes a plurality of memory cell units each composed of a plurality of memory cells; each of said write circuits is provided for a corresponding one of said memory cell units; and said write circuits further comprise a write control circuit for activating one of said write circuits in sequence, to enable a write operation through said boost circuit having a small driving capability.
Claim 36
Dependent Claim
45 words
The semiconductor memory device of claim 19, further comprising operating point control means for setting an operating point of the respective transistor in each of said memory cells so as to minimize write current flowing therethrough in a writing operation, for reduction of current consumption.
Claim 37
Dependent Claim
45 words
The semiconductor memory device of claim 20, further comprising operating point control means for setting an operating point of the respective transistor in each of said memory cells so as to minimize write current flowing therethrough in a writing operation, for reduction of current consumption.
Claim 38
Dependent Claim
45 words
The semiconductor memory device of claim 21, further comprising operating point control means for setting an operating point of the respective transistor in each of said memory cells so as to minimize write current flowing therethrough in a writing operation, for reduction of current consumption.
Claim 39
Dependent Claim
198 words
A semiconductor memory device having a memory cell array which includes a plurality of memory cells arranged into a matrix pattern on a main chip, data being written in, read from, and erased from at least one selected memory cell formed of a transistor, data being respectively written in and erased from the at least one selected memory cell on the basis of a write voltage and an erased voltage obtained by boosting an internal supply voltage, said semiconductor memory device comprising: an erase circuit for applying an erase voltage to the at least one selected memory cell to erase data therefrom; a boost circuit for boosting the internal supply voltage to generate the erase voltage and outputting the generated erase voltage through a boosted voltage output terminal; an on-chip pad terminal for outputting an output of said boost circuit; an outer terminal electrically connected to the on-chip pad terminal and configured to connect an external circuit element thereto; and a capacitor externally connected to said outer terminal and configured to receive an electric charge of said boost circuit, data being erased from the at least one selected memory cell by discharging the electric charge of said capacitor.
Claim 40
Dependent Claim
198 words
A semiconductor memory device having a memory cell array which includes a plurality of memory cells arranged into a matrix pattern on a main chip, data being written in, read from, and erased from at least one selected memory cell formed of a transistor, data being respectively written in and erased from the at least one selected memory cell on the basis of a write voltage and an erased voltage obtained by boosting an internal supply voltage, said semiconductor memory device comprising: an erase circuit for applying an erase voltage to the at least one selected memory cell to erase data therefrom; a boost circuit for boosting the internal supply voltage to generate the erase voltage and outputting the generated erase voltage through a boosted voltage output terminal; an on-chip pad terminal for outputting an output of said boost circuit; an outer terminal electrically connected to the on-chip pad terminal and configured to connect an external circuit element thereto; and a capacitor externally connected to said outer terminal and configured to receive an electric charge of said boost circuit, data being erased from the at least one selected memory cell by discharging the electric charge of said capacitor.
Claim 41
Dependent Claim
29 words
The semiconductor memory device of claim 37, wherein said outer terminal is an external lead terminal projecting from a package, and said capacitor being connected externally to the package.
Claim 42
Dependent Claim
37 words
The semiconductor memory device of claim 37, wherein said capacitor is formed on or in a capacitor chip different from the main chip, the capacitor chip and the main chip being both assembled together within the package.
Claim 43
Dependent Claim
31 words
The semiconductor memory device of claim 39, wherein said on-chip pad terminal formed on the main chip is connected to said capacitor formed on the capacitor chip through a bonding wire.
Claim 44
Dependent Claim
27 words
The semiconductor memory device of claim 39, wherein said capacitor is formed by stacking a plurality of insulating films and a plurality of poly silicon layers alternately.
Claim 45
Dependent Claim
26 words
The semiconductor memory device of claim 39, wherein said capacitor includes a plurality of trenches formed in a semiconductor substrate and filled with an insulating substance.
Claim 46
Dependent Claim
46 words
The semiconductor memory device of claim 37, further comprising an erase-enable status discriminate circuit for discriminating whether data can be erased from each memory cell and outputting a discriminate signal indicative thereof, data being erased from each memory call on the basis of the discriminate signal.
Claim 47
Dependent Claim
46 words
The semiconductor memory device of claim 38, further comprising an erase-enable status discriminate circuit for discriminating whether data can be erased from each memory cell and outputting a discriminate signal indicative thereof, data being erased from each memory cell on the basis of the discriminate signal.
Claim 48
Dependent Claim
45 words
The semiconductor memory device of claim 39, further comprising an erase-enable status discriminate circuit for discriminating whether data can be erased from each memory cell and outputting a discriminate signal indicative thereof, data being from each memory cell on the basis of the discriminate signal.
Claim 49
Dependent Claim
33 words
The semiconductor memory device of claim 37, further comprising an erase timer responsive to an erase start signal, for setting the semiconductor memory device to an erase operation status for a constant time.
Claim 50
Dependent Claim
33 words
The semiconductor memory device of claim 38, further comprising an erase timer responsive to an erase start signal, for setting the semiconductor memory device to an erase operation status for a constant time.
Claim 51
Dependent Claim
33 words
The semiconductor memory device of claim 39, further comprising an erase timer responsive to an erase start signal, for setting the semiconductor memory device to an erase operation status for a constant time.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-05-21 | 1999-11-20 | 2000-05-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-05-21 | 2003-11-20 | 2004-05-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-05-21 | 2007-11-20 | 2008-05-21 | $7700.00 | Window Closed / Lapsed |