US4572972A
Expired / Lapsed
US
⏱️ 0.0 years remaining
CMOS Logic circuits with all pull-up transistors integrated in separate chip from all pull-down transistors
Assignee: AT&T Labs Inc
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Filing: 1983-01-18
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Granted: 1986-02-25
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Expires: 2003-01-18
Abstract
Abstract An integrated circuit chip with a preferred ground structure and including only pull-down transistors (on-chip) is operated by means of an off-chip pull-up transistor arrangement for precharging the data bus to logic high. The arrangement exhibits relatively low noise characteristics allowing relatively high frequency operation without generating noise voltages which exceed FET threshold voltages.
Inventors
- 👤 Masakazu Shoji
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 06:14
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/427; H10W72/00; H10W72/90; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
88 words
An IC chip having front and back surfaces, said chip including a first BUS on said front surface, said first BUS being connected through a conductive substrate region of said chip to a metallic layer which coats said back surface, a plurality of pull-down transistors being integrated in said chip and being connected for pulling the voltage levels of bit lines in an external BUS down to the voltage level of the first BUS in response to logic signals applied to the control terminals of the pull-down transistors.
Claim 2
Dependent Claim
88 words
An IC chip having front and back surfaces, said chip including a first BUS on said front surface, said first BUS being connected through a conductive substrate region of said chip to a metallic layer which coats said back surface, a plurality of pull-down transistors being integrated in said chip and being connected for pulling the voltage levels of bit lines in an external BUS down to the voltage level of the first BUS in response to logic signals applied to the control terminals of the pull-down transistors.
Claim 3
Dependent Claim
61 words
An IC chip in accordance with claim 1 wherein said first BUS comprises a ground BUS and said external BUS comprises a Data BUS, and a second chip having integrated therein an equal plurality of pull-up transistors connectable to the external BUS, whereby each of the pull-up transistors together with a corresponding one of the pull-down transistor forms a CMOS inverter.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-02-24 | 1989-08-26 | 1990-02-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-02-24 | 1993-08-26 | 1994-02-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-02-24 | 1997-08-26 | 1998-02-25 | $7700.00 | Window Closed / Lapsed |