Process for transmitting signals between two chips with high-speed complementary MOS circuits

Claim 2

A process for transmitting signals between first and second semiconductor chips each having high-speed complementary MOS circuits, comprising the steps of providing an output stage on the first chip for transforming the voltage level of a signal from a connected MOS circuit to a relatively low level voltage, providing a connection line for transmitting the relatively low level voltage to the second chip, whereby the connection line is connected with the output stage on the first chip, and providing an input stage on a second chip for amplifying the low level voltage to the original voltage level, whereby said input stage is connected with the connection line and the signal is restored to its original level for connection to a subsequent MOS circuit on the second chip.

Claim 3

The method according to claim 1, including the step of providing a pair of connecting lines for interconnecting the output stage of the first chip and the input stage of the second chip, whereby complementary signals may be transmitted over the connection lines between the two chips.

Claim 4

The method according to claim 2, including the step of providing a pair of impedances on said second chip connecting with said transmission lines, said impedances having values of impedance which match the characteristic impedance of both of said connecting lines.

Claim 5

The process according to claim 1, including the step of using a source follower to transform the voltage level from the MOS circuit on the first chip to a relatively low level.

Claim 6

Apparatus for transmitting signals between first and second semiconductor chips with high-speed complementary MOS circuits, comprising an output stage associated with the first chip, said output stage including an inverter, the input of said inverter being connected to receive a signal from a MOS circuit of the first chip, an output transistor having its input connected to the output of said inverter and its output connected to a first transmission line interconnecting the first and second chips, and a further output transistor having its input connected to receive said signal from said MOS circuit of the first chip and having its output connected to a second transmission line interconnecting the first and second chips, whereby complementary signals are provided on the two connecting lines, an input stage on the second chip, said input stage including an amplifier adapted to receive a signal connected from the first chip, and an inverter interconnected between said amplifier and a complementary MOS circuit located on the second chip.

Claim 7

Apparatus for transmitting signals between first and second semiconductor chips with high-speed complementary MOS circuits, comprising an output stage associated with the first chip, said output stage including an inverter, the input of said inverter being connected to receive a signal from a MOS circuit of the first chip, an output transistor having its input connected to the output of said inverter and its output connected to a first transmission line interconnecting the first and second chips, and a further output transistor having its input connected to receive said signal from said MOS circuit of the first chip and having its output connected to a second transmission line interconnecting the first and second chips, whereby complementary signals are provided on the two connecting lines, an input stage on the second chip, said input stage including an amplifier adapted to receive a signal connected from the first chip, and an inverter interconnected between said amplifier and a complementary MOS circuit located on the second chip.

Claim 8

Apparatus according to claim 5, wherein said output transistors are each connected as a source follower with its source terminal connected to one of said transmission lines.

Claim 9

Apparatus according to claim 5, wherein said amplifier comprises a pulsed, bistable trigger.

Claim 10

Apparatus according to claim 5, wherein said amplifier comprises a monostable trigger.

Claim 11

Apparatus according to claim 5, wherein said connection between said first and second semiconductor chips comprises a pair of connecting lines for transmitting complementary signals between said chips, said input stage being connected to said connecting lines, and a pair of impedances connected to said connecting lines having values of impedance which match the characteristic impedance of both of the connecting lines.

Claim 12

For use in connection with a process for transmitting signals between two semiconductor chips with high-speed complementary MOS circuits, a combination comprising an input stage associated with one of said semiconductor chips, said input stage including an amplifier adapted to receive a signal connected from the other semiconductor chip, an inverter interconnected between said amplifier and a complementary MOS circuit located on said one chip, and a connection between said one chip and said other chip comprising a pair of connecting lines for transmitting complementary signals between said chips, said input stage being connected to said connecting lines, and a pair of impedances connected to said connecting lines having values of impedance which match the characteristic impedance of both of the connecting lines.

Claim 13

For use in connection with a process for transmitting signals between two semiconductor chips with high-speed complementary MOS circuits, a combination comprising an input stage associated with one of said semiconductor chips, said input stage including an amplifier adapted to receive a signal connected from the other semiconductor chip, an inverter interconnected between said amplifier and a complementary MOS circuit located on said one chip, and a connection between said one chip and said other chip comprising a pair of connecting lines for transmitting complementary signals between said chips, said input stage being connected to said connecting lines, and a pair of impedances connected to said connecting lines having values of impedance which match the characteristic impedance of both of the connecting lines.