US3731114A — Two phase logic circuit

Claim 1

Independent Claim 272 words

A logic circuit comprising: first gate means having input and output terminals; first control signal supplying means connected to said first gate means to control operation thereof; second gate means having input and output terminals; said input terminal of said second gate means connected to said output terminal of said first gate means; and second control signal supplying means for supplying signals outof-phase with said first control signal supplying means; said second gate means includes first, second, third and fourth semiconductor devices of the same conductivity type and each having a conduction path and a control electrode for controlling the conduction of said conduction path; said first and second semiconductor devices having the conduction paths thereof connected in parallel with each other; said third and fourth semiconductor devices having the conduction paths thereof connected together in series and said third semiconductor device connected directly in series with the parallel connected conduction paths of said first and second semiconductor devices; the opposite ends of the series circuit comprising the series connected conduction paths connected to said first control signal supplying means; said control electrodes of said second and fourth semiconductor devices connected to said first control signal supplying means; said control electrode of said first semiconductor device connected to said second control signal supplying means; said control electrode of said third semiconductor device connected to said output terminal of said first gate means; said output terminal of said second gate means connected to the common junction of the conduction paths of said third and fourth semiconductor devices; and said first and second gate means producing complementary output signals at the output terminals thereof.

Claim 2

Dependent Claim 272 words

A logic circuit comprising: first gate means having input and output terminals; first control signal supplying means connected to said first gate means to control operation thereof; second gate means having input and output terminals; said input terminal of said second gate means connected to said output terminal of said first gate means; and second control signal supplying means for supplying signals outof-phase with said first control signal supplying means; said second gate means includes first, second, third and fourth semiconductor devices of the same conductivity type and each having a conduction path and a control electrode for controlling the conduction of said conduction path; said first and second semiconductor devices having the conduction paths thereof connected in parallel with each other; said third and fourth semiconductor devices having the conduction paths thereof connected together in series and said third semiconductor device connected directly in series with the parallel connected conduction paths of said first and second semiconductor devices; the opposite ends of the series circuit comprising the series connected conduction paths connected to said first control signal supplying means; said control electrodes of said second and fourth semiconductor devices connected to said first control signal supplying means; said control electrode of said first semiconductor device connected to said second control signal supplying means; said control electrode of said third semiconductor device connected to said output terminal of said first gate means; said output terminal of said second gate means connected to the common junction of the conduction paths of said third and fourth semiconductor devices; and said first and second gate means producing complementary output signals at the output terminals thereof.

Claim 3

Dependent Claim 167 words

The logic circuit recited in claim 1 wherein said first gate means includes fifth, sixth, and seventh semiconductor devices of the same conductivity type as said first semiconductor device; each of said semiconductor devices having a conduction path and a control electrode for controlling the conduction of the conduction path; said fifth and sixth semiconductor devices having the conduction paths thereof connecteD in series; said output terminal connected to the common junction of the conduction paths of said fifth and sixth semiconductor devices; the opposite ends of the series connected conduction paths connected to said first control signal supplying means; said seventh semiconductor device having the conduction path thereof connected from said input terminal to said control electrode of said sixth semiconductor device to supply signals from said input terminal to the control electrode of said sixth semiconductor device when said seventh semiconductor device is conductive; and the control electrodes of said fifth and seventh semiconductor devices connected together and to said first control signal supplying means.

Claim 4

Dependent Claim 118 words

The logic circuit recited in claim 1 including a pair of output gate means: each of said output gate means including one semiconductor device having a conduction path and a control electrode for controlling the conduction of said conduction path; each of said semiconductors having the conduction path thereof connected from a different one of the output terminals of said first and second gate means to a different output device; and each of said semiconductors having the control electrode thereof connected to said second control signal supplying means so that signals are transferred from said first and second gate means to said output devices in synchronism according to the signal supplied by said second control signal supplying means.

Claim 5

Dependent Claim 195 words

The logic circuit recited in claim 1 wherein said second gate means includes eighth, ninth, and tenth semiconductor devices of the same conductivity type as said first semiconductor device and each having a conduction path and a control electrode for controlling the conduction of said conduction path; said eighth semiconductor device having the conduction path thereof connected in series between the conduction paths of said third and second semiconductor devices; said ninth and tenth semiconductor devices having the conduction paths thereof connected in series in the order presented from said first control signal supplying means to said output terminal of said second gate means, whereby said series connected conduction paths of said ninth and tenth semiconductor devices are effectively in parallel with the series connected conduction paths of said first, third and eight semiconductor devices; the control electrode of said ninth semiconductor device connected to said first control signal supplying means; input means connected to the control electrodes of said eighth and tenth semiconductor devices; and means interconnecting the series connected conduction paths to produce a gating function which is controlled by the signals supplied thereto by said input means and said first gate means.

Claim 6

Dependent Claim 176 words

A logic circuit including: first and second clock signal sources for producing clock signals of different phase relation; first semiconductor means connected to said first clock signal source and for charging an output node to a predetermined condition in response to a clock signal of one level from said first clock signal source; second semiconductor means connected to said first clock signal source and for charging an intermediate node to a predetermined condition in response to a clock signal of said one level from said first clock signal source; third semiconductor means connected to both of said first first and second clock signal sources and for charging said intermediate node to a different predetermined condition in response to a clock signal of a second level from said first clock signal source and a clock signal of one level from said second clock signal source; and fourth semiconductor means connected between said intermediate node and said output node to selectively effect a signal transfer therebetween as a function of the control signal supplied to said fourth semiconductor.

Claim 7

Dependent Claim 176 words

A logic circuit including: first and second clock signal sources for producing clock signals of different phase relation; first semiconductor means connected to said first clock signal source and for charging an output node to a predetermined condition in response to a clock signal of one level from said first clock signal source; second semiconductor means connected to said first clock signal source and for charging an intermediate node to a predetermined condition in response to a clock signal of said one level from said first clock signal source; third semiconductor means connected to both of said first first and second clock signal sources and for charging said intermediate node to a different predetermined condition in response to a clock signal of a second level from said first clock signal source and a clock signal of one level from said second clock signal source; and fourth semiconductor means connected between said intermediate node and said output node to selectively effect a signal transfer therebetween as a function of the control signal supplied to said fourth semiconductor.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1976-04-30	1976-10-30	1977-05-01	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1980-04-30	1980-10-30	1981-05-01	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1984-04-30	1984-10-30	1985-05-01	$7700.00	Window Closed / Lapsed

Two phase logic circuit

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