Dynamic shift register

Claim 2

A single-bit delay register comprising a pair of identical charge transfer stages, each of said stages having a data input terminal and a clock input terminal and an output terminal, the output terminal of the first of said stages being serially connected to the input terminal of the second of said stages, each of said stages including first and second clock-controlled transistor switch means and a data-controlled transistor switch means, said first and second clock-controlled transistor switch means having a common connection to said clock terminal, one of said clock-controlled transistor switch means connected in parallel with said data-controlled transistor switch means between said clock terminal and said output terminal, a clock signal source to the clock terminal of said second stage being out of phase with a clock signal source of said first stage such that said first and second stages are alternately triggered by out of phase clock pulses for transfer of a single information bit.

Claim 3

The register of claim 6 wherein each of said stages includes a charge-storing means; each of said switch means having a pair of output terminals and a control terminal; the output terminals of said first switch means coupled between said data input terminal and the control terminal of said data-controlled switch means; the output terminals of both said second switch means and said data-coNtrolled switch means being connected in parallel between said clock input terminal and said stage output terminal; the control terminals of said first and second switch means coupled to said clock input terminal; and said charge-storing means coupled between the control means of said data switch means and ground such that during a first voltage state of said clock source said stage output terminal is charged thereto and a data signal is transferred from said data input terminal to said charge-storing means, and during a second voltage state of said clock source said stage output terminal is selectively discharged to said second voltage state in accordance with data input stored in said charge-storing means so as to provide an output response which is inverted with respect to said data input.

Claim 4

The register of claim 1 wherein all said switch means are field-effect transistors with substantially identical geometric configurations, and said charge-storing means includes the gate capacitance of said data controlled switch means.

Claim 5

The register of claim 3 including a charge transfer switch in combination with said first transfer switch including another field-effect transistor having its gate terminal in connection to said second clock source and its output terminals connected to the gate of said data-controlled transistor switch means and to another output terminal such that upon operation of said single bit stage a charge proportional to the input data to said single bit stage is transferred to said other output terminal in synchronization with the transfer to the output of said single bit stage.