Programmable read only memory device

Abstract

Abstract PURPOSE:To make it possible to securely write the data even when the write voltage is low, to make the peripheral transistor smaller and to improve the high integration of the memory device by making the high voltage impressed to the control gate of the floating gate transistor later than the high voltage impressed to the drain. CONSTITUTION:The circuit of the column decoder is provided with a gate G2 where non-inversion and inversion address signals ADD are inputted, a high breakdown strengh depression type transistor Q15, a high breakdown strength nondoze type transistor Q6 and a high deep depression transistor Q17. A program signal PGM is supplied directly to a transistor Q16 of the column decoder, a program signal DPGM is supplied to the gate of a transistor Q13 of the row decoder and the rise-up time of the row selection signal and the column selection signal is different. First, a column selection signal CLM rises up from a Vcc level to a Vpp level and after that, a row selection signal ROW rises up from a Vcc level of a Vpp level. Thus, even when a write voltage Vpp is comparatively low, the data is written securely.

Inventors

• 👤 Manabu Tsuchida
• 👤 学 土田
• 👤 Masanobu Yoshida
• 👤 吉田　正信

Bibliographic Details