Patent US5517659A successfully refreshed from Google Patents.
US5517659A
Expired / Lapsed
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Multiplexed status and diagnostic pins in a microprocessor with on-chip caches
Assignee: Renesas Electronics America Inc
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Filing: 1994-05-11
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Granted: 1996-05-14
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Expires: 2014-05-11
Abstract
Abstract In a microprocessor, two output pins are dedicated to providing information to assist in diagnosing problems relating to internal instruction and data caches or the software executing in the caches. The information on the pins is time-multiplexed. In a first phase, the pins indicate whether the data or instruction cache is accessed and whether a cache miss has occurred. In a second phase, the pins carry signals identifying the address reference which resulted in a cache miss.
Inventors
- 👤 Philip A. Bourekas
- 👤 Yeshayahu Mor
- 👤 Scott Revak
- 👤 Avigdor Willenz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 05:40
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G06F11/261; G06F11/2205; G06F11/2236; G06F11/30; G06F11/34; G06F11/3466; G06F11/349; G06F2201/00; G06F2201/885
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
360 words
An arrangement for providing information concerning operation of a cache memory in a microprocessor, said arrangement comprising: a microprocessor formed on a semiconductor chip, said microprocessor containing a central processing unit (CPU) and a cache memory, an output of said CPU being connected to said cache memory; and a main memory external to said chip, an output of said microprocessor being connected to said main memory; wherein said microprocessor reads a word from said cache memory using an address which contains a first bit which is not contained in an address used by said microprocessor in reading digital information which contains said word from said main memory upon a cache miss; said arrangement further comprising: a multiplexer having a first input connected to a first output of said CPU, said first input receiving a signal indicating whether an address accessed by said microprocessor is cacheable or uncacheable, and having a second input connected to a second output of said CPU, said second input receiving said first bit, an output of said multiplexer being connected to a pin of said semiconductor chip; wherein said cache memory comprises an instruction cache and a data cache, said arrangement further comprising a second multiplexer having a first input connected to a third output of said CPU, said first input of said second multiplexer receiving a signal indicating whether said microprocessor is accessing said instruction cache or said data cache, said second multiplexer further having a second input connected to a fourth output of said CPU, said second input of said second multiplexer receiving a second bit used by said microprocessor in reading said word from said cache memory but not used by said microprocessor in reading said digital information which contains said word from said main memory upon said cache miss, an output of said second multiplexer being connected to a second pin of said semiconductor chip; and wherein a select/control input of each of said first and second multiplexers is connected to a line for holding a first signal during an address phase of a bus in said microprocessor and a second signal during a data phase of said bus in said microprocessor.
Claim 2
Dependent Claim
360 words
An arrangement for providing information concerning operation of a cache memory in a microprocessor, said arrangement comprising: a microprocessor formed on a semiconductor chip, said microprocessor containing a central processing unit (CPU) and a cache memory, an output of said CPU being connected to said cache memory; and a main memory external to said chip, an output of said microprocessor being connected to said main memory; wherein said microprocessor reads a word from said cache memory using an address which contains a first bit which is not contained in an address used by said microprocessor in reading digital information which contains said word from said main memory upon a cache miss; said arrangement further comprising: a multiplexer having a first input connected to a first output of said CPU, said first input receiving a signal indicating whether an address accessed by said microprocessor is cacheable or uncacheable, and having a second input connected to a second output of said CPU, said second input receiving said first bit, an output of said multiplexer being connected to a pin of said semiconductor chip; wherein said cache memory comprises an instruction cache and a data cache, said arrangement further comprising a second multiplexer having a first input connected to a third output of said CPU, said first input of said second multiplexer receiving a signal indicating whether said microprocessor is accessing said instruction cache or said data cache, said second multiplexer further having a second input connected to a fourth output of said CPU, said second input of said second multiplexer receiving a second bit used by said microprocessor in reading said word from said cache memory but not used by said microprocessor in reading said digital information which contains said word from said main memory upon said cache miss, an output of said second multiplexer being connected to a second pin of said semiconductor chip; and wherein a select/control input of each of said first and second multiplexers is connected to a line for holding a first signal during an address phase of a bus in said microprocessor and a second signal during a data phase of said bus in said microprocessor.
Claim 3
Dependent Claim
52 words
The arrangement of claim 1 wherein each of said first and second multiplexers is adapted such that said first input thereof is selected when said first signal is present at said select/control input thereof and said second input thereof is selected when said second signal is present at said select/control input thereof.
Claim 4
Dependent Claim
18 words
The arrangement of claim 1 wherein said first signal and said second signal occur in a time-multiplexed fashion.
Claim 5
Dependent Claim
192 words
An arrangement for providing diagnostic information concerning the operation of a cache memory in a microprocessor, said arrangement comprising: a microprocessor formed on a semiconductor chip, said microprocessor containing a central processing unit (CPU) and a cache memory, an output of said CPU being connected to said cache memory; and a main memory external to said chip, an output of said microprocessor being connected to said main memory; wherein said CPU reads a word from said cache memory using an address which contains a first bit which is not contained in an address used by said CPU in reading digital information which contains said word from said main memory upon a cache miss; said semiconductor chip further comprising: a multiplexer having a first input connected to a first output of said CPU, said first input receiving a signal indicating whether an address accessed by said microprocessor is cacheable or uncacheable, and having a second input connected to a second output of said CPU, said second input receiving said first bit, an output of said multiplexer being connected to a pin of said semiconductor chip, said pin being for providing said diagnostic information.
Claim 6
Dependent Claim
192 words
An arrangement for providing diagnostic information concerning the operation of a cache memory in a microprocessor, said arrangement comprising: a microprocessor formed on a semiconductor chip, said microprocessor containing a central processing unit (CPU) and a cache memory, an output of said CPU being connected to said cache memory; and a main memory external to said chip, an output of said microprocessor being connected to said main memory; wherein said CPU reads a word from said cache memory using an address which contains a first bit which is not contained in an address used by said CPU in reading digital information which contains said word from said main memory upon a cache miss; said semiconductor chip further comprising: a multiplexer having a first input connected to a first output of said CPU, said first input receiving a signal indicating whether an address accessed by said microprocessor is cacheable or uncacheable, and having a second input connected to a second output of said CPU, said second input receiving said first bit, an output of said multiplexer being connected to a pin of said semiconductor chip, said pin being for providing said diagnostic information.
Claim 7
Dependent Claim
137 words
The arrangement of claim 4 wherein said cache memory comprises an instruction cache and a data cache, said arrangement further comprising a second multiplexer having a first input connected to a third output of said CPU, said first input of said second multiplexer receiving a signal indicating whether said microprocessor is accessing said instruction cache or said data cache, said second multiplexer further having a second input connected to a fourth output of said CPU, said second input of said second multiplexer receiving a second bit used by said microprocessor in reading said word from said cache memory but not used by said microprocessor in reading said digital information which contains said word from said main memory upon said cache miss, an output of said second multiplexer being connected to a second pin of said semiconductor chip.
Claim 8
Dependent Claim
167 words
An arrangement for providing diagnostic information about the operation of a cache memory in a microprocessor, said microprocessor being formed on a semiconductor chip and being connected to a main memory external to said chip, a central processing unit (CPU) in said microprocessor accessing a word from said cache memory using an address which contains at least two bits which are not contained in an address used by said CPU to access digital information which contains said word from said main memory upon a cache miss, said semiconductor chip comprising at least two multiplexers, each of said at least two multiplexers having a first input which receives from said CPU certain information concerning the operation of said cache memory and having a second input which receives from said CPU one of said at least two bits, said at least two multiplexers having outputs which are connected, respectively, to at least two pins of said semiconductor chip, said at least two pins being for providing said diagnostic information.
Claim 9
Dependent Claim
167 words
An arrangement for providing diagnostic information about the operation of a cache memory in a microprocessor, said microprocessor being formed on a semiconductor chip and being connected to a main memory external to said chip, a central processing unit (CPU) in said microprocessor accessing a word from said cache memory using an address which contains at least two bits which are not contained in an address used by said CPU to access digital information which contains said word from said main memory upon a cache miss, said semiconductor chip comprising at least two multiplexers, each of said at least two multiplexers having a first input which receives from said CPU certain information concerning the operation of said cache memory and having a second input which receives from said CPU one of said at least two bits, said at least two multiplexers having outputs which are connected, respectively, to at least two pins of said semiconductor chip, said at least two pins being for providing said diagnostic information.
Claim 10
Dependent Claim
20 words
The arrangement of claim 6 wherein said at least two bits identify a word sought in a cache memory miss.
Claim 11
Dependent Claim
24 words
The arrangement of claim 6 wherein the first input of each of said at least two multiplexers receives access type information from said CPU.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-05-14 | 1999-11-13 | 2000-05-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-05-14 | 2003-11-13 | 2004-05-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-05-14 | 2007-11-13 | 2008-05-14 | $7700.00 | Window Closed / Lapsed |