Method of forming a transistor

Claim 1

A method of forming a transistor for an integrated circuit, comprising: providing a semiconductor substrate for an integrated circuit having a surface with a device well region of a first conductivity type defined therein; providing a tapered body of a first dielectric material masking a selected region of the substrate surface, the tapered body having sidewalls tapering outwardly from the selected region on the substrate towards a top surface of the tapered body; providing a layer of an other dielectric material forming sidewall spacers on sidewalls of the tapered body; providing a layer of a first conductive material over regions of the substrate adjacent the tapered body, said layer having a surface coplanar with the top surface of the tapered body, to form first contact electrodes with the underlying substrate surface; selectively removing the tapered body of the first dielectric material from the substrate thereby exposing sidewall spacers of the other dielectric material to define a tapered opening exposing said selected region of the substrate within the opening; forming a second contact electrode by providing a layer of a second conductive material within the tapered opening, isolated from the first conductive layer by the dielectric sidewall spacers; planarizing the resulting structure to form a fully planarized surface providing coplanar contact areas on the first and second contact electrodes.

Claim 2

A method of forming a transistor for an integrated circuit, comprising: providing a semiconductor substrate for an integrated circuit having a surface with a device well region of a first conductivity type defined therein; providing a tapered body of a first dielectric material masking a selected region of the substrate surface, the tapered body having sidewalls tapering outwardly from the selected region on the substrate towards a top surface of the tapered body; providing a layer of an other dielectric material forming sidewall spacers on sidewalls of the tapered body; providing a layer of a first conductive material over regions of the substrate adjacent the tapered body, said layer having a surface coplanar with the top surface of the tapered body, to form first contact electrodes with the underlying substrate surface; selectively removing the tapered body of the first dielectric material from the substrate thereby exposing sidewall spacers of the other dielectric material to define a tapered opening exposing said selected region of the substrate within the opening; forming a second contact electrode by providing a layer of a second conductive material within the tapered opening, isolated from the first conductive layer by the dielectric sidewall spacers; planarizing the resulting structure to form a fully planarized surface providing coplanar contact areas on the first and second contact electrodes.

Claim 7

A method of forming a bipolar transistor for an integrated circuit, comprising: providing a semiconductor substrate for an integrated circuit comprising a surface having defined therein a device well region of a first conductivity type; providing a masking layer of a dielectric material overall; patterning and etching the masking layer to define a tapered opening therethrough exposing a selected region of the substrate within a bottom of the tapered opening, said selected region defining a base-emitter junction area of the bipolar transistor; providing a tapered body of a second dielectric material by filling the tapered opening coplanar with a surrounding surface of the masking layer; selectively removing the masking layer, leaving exposed tapered sidewalls of the body of the second dielectric material, the tapered body of the second dielectric material thereby masking the selected region of the substrate; providing a layer of a first conductive material over exposed regions of the substrate adjacent the tapered sidewalls of the dielectric body to form base contact electrodes with the underlying substrate; selectively removing the tapered body of the second dielectric and exposing sidewalls of the first conductive layer to define a tapered emitter opening therein; providing a dielectric isolation layer comprising sidewall spacers on exposed sidewalls of the first conductive layer; forming an intrinsic base region of a second conductivity type within the opening; forming an emitter structure within the emitter opening comprising of a layer of an emitter material of the first conductivity type filling the opening in the first conductive layer to a level coplanar with the planarized surface of the first conductive layer, the emitter material being isolated from the first conductive layer by the sidewall spacers and forming a base-emitter junction with the underlying base region within the opening.

Claim 8

A method of forming a bipolar transistor for an integrated circuit, comprising: providing a semiconductor substrate for an integrated circuit comprising a surface having defined therein a device well region of a first conductivity type; providing a masking layer of a dielectric material overall; patterning and etching the masking layer to define a tapered opening therethrough exposing a selected region of the substrate within a bottom of the tapered opening, said selected region defining a base-emitter junction area of the bipolar transistor; providing a tapered body of a second dielectric material by filling the tapered opening coplanar with a surrounding surface of the masking layer; selectively removing the masking layer, leaving exposed tapered sidewalls of the body of the second dielectric material, the tapered body of the second dielectric material thereby masking the selected region of the substrate; providing a layer of a first conductive material over exposed regions of the substrate adjacent the tapered sidewalls of the dielectric body to form base contact electrodes with the underlying substrate; selectively removing the tapered body of the second dielectric and exposing sidewalls of the first conductive layer to define a tapered emitter opening therein; providing a dielectric isolation layer comprising sidewall spacers on exposed sidewalls of the first conductive layer; forming an intrinsic base region of a second conductivity type within the opening; forming an emitter structure within the emitter opening comprising of a layer of an emitter material of the first conductivity type filling the opening in the first conductive layer to a level coplanar with the planarized surface of the first conductive layer, the emitter material being isolated from the first conductive layer by the sidewall spacers and forming a base-emitter junction with the underlying base region within the opening.