Self-aligned bipolar transistor process

Claim 2

A process for forming a self-aligned bipolar transistor in a semiconductor device, comprising the steps of: providing a semiconductor substrate having an active device region and an oxide layer overlying the active device region; forming a patterned dielectric layer overlying the active device region and the oxide layer and having an opening bounded by a wall which exposes a portion of the oxide layer; forming a TiN sidewall spacer on the wall of the patterned dielectric layer; selectively doping the active device region to form a first base region using the TiN sidewall spacer and the patterned dielectric layer as a doping mask; removing the exposed portion of the oxide layer within the opening using the TiN sidewall spacer and the patterned dielectric layer as an etch mask to form an exposed portion of the active device region; forming an emitter electrode by selective deposition of a predetermined material on the exposed portion of the active device region; removing the patterned dielectric layer; doping the active device region to form a second base region; forming a metal silicide contact to each of the second base region and the emitter electrode; and removing the TiN sidewall spacer.

Claim 3

The process of claim 1 further comprising the step of doping the active device region to form a link region adjoining the first and second base regions, following the step of removing the TiN sidewall spacer.

Claim 4

The process of claim 1 wherein the step of forming an emitter electrode comprises forming an emitter electrode by selective deposition of silicon.

Claim 5

The process of claim 3 wherein the step of forming an emitter electrode comprises forming an emitter electrode by selective deposition of insitu doped N-type silicon.

Claim 6

The process of claim 1 wherein the step of forming a patterned dielectric layer comprises forming a patterned Si 3 N 4 layer.

Claim 7

The process of claim 1 wherein the step of forming metal silicide contacts comprises forming one of either cobalt silicide or titanium silicide contacts.

Claim 8

A process for forming a self-aligned bipolar transistor in a semiconductor device, comprising the steps of: providing a substrate having an active device region; forming a patterned masking layer overlying the active device region and having an opening therein; forming a sidewall spacer within the opening of the patterned masking layer; selectively doping the active device region to form a first base region using the sidewall spacer and the patterned masking layer as a doping mask; forming an emitter electrode by selective deposition of a predetermined material which overlies the first base region; doping the active device region to form a second base region; forming a metal silicide contact to each of the second base region and the emitter electrode; and removing the sidewall spacer.

Claim 9

A process for forming a self-aligned bipolar transistor in a semiconductor device, comprising the steps of: providing a substrate having an active device region; forming a patterned masking layer overlying the active device region and having an opening therein; forming a sidewall spacer within the opening of the patterned masking layer; selectively doping the active device region to form a first base region using the sidewall spacer and the patterned masking layer as a doping mask; forming an emitter electrode by selective deposition of a predetermined material which overlies the first base region; doping the active device region to form a second base region; forming a metal silicide contact to each of the second base region and the emitter electrode; and removing the sidewall spacer.

Claim 10

The process of claim 7 wherein the step of forming an emitter electrode comprises forming an emitter electrode by selective deposition of silicon.

Claim 11

The process of claim 7 further comprising the step of selectively doping the active device region to form an emitter region using the sidewall spacer and the patterned masking layer as a doping mask, prior to the step of forming an emitter electrode.

Claim 12

The process of claim 7 further comprising the step of doping the active device region to form a link region adjoining the first and second base regions.

Claim 13

The process of claim 7 wherein the step of forming metal silicide contacts comprises forming one of either cobalt silicide or titanium silicide.

Claim 14

The process of claim 7 wherein the step of forming a sidewall spacer comprises forming a TiN sidewall spacer within the opening of the patterned masking layer.

Claim 15

A process for forming a self-aligned bipolar transistor in a semiconductor device, comprising the steps of: providing a substrate having an active device region and an oxide layer overlying the active device region; forming a patterned masking layer overlying the active device region and having an opening therein bounded by a wall; forming a TiN sidewall spacer on the wall of the patterned masking layer; selectively doping the active device region to form a first base region using the TiN sidewall spacer and the patterned masking layer as a doping mask; removing a first portion of the oxide layer within the opening using the TiN sidewall spacer and the patterned masking layer as an etch mask to form a first exposed portion of the active device region; forming an emitter electrode by selective deposition of silicon on the first exposed portion of the active device region; removing the patterned masking layer and a second portion of the oxide layer to form a second exposed portion of the active device region; doping the second exposed portion of the active device region to form a second base region; forming metal silicide contacts to the second base region and the emitter electrode; removing the TiN sidewall spacer; and doping the active device region to form a link region which connects the first and second base regions.

Claim 16

A process for forming a self-aligned bipolar transistor in a semiconductor device, comprising the steps of: providing a substrate having an active device region and an oxide layer overlying the active device region; forming a patterned masking layer overlying the active device region and having an opening therein bounded by a wall; forming a TiN sidewall spacer on the wall of the patterned masking layer; selectively doping the active device region to form a first base region using the TiN sidewall spacer and the patterned masking layer as a doping mask; removing a first portion of the oxide layer within the opening using the TiN sidewall spacer and the patterned masking layer as an etch mask to form a first exposed portion of the active device region; forming an emitter electrode by selective deposition of silicon on the first exposed portion of the active device region; removing the patterned masking layer and a second portion of the oxide layer to form a second exposed portion of the active device region; doping the second exposed portion of the active device region to form a second base region; forming metal silicide contacts to the second base region and the emitter electrode; removing the TiN sidewall spacer; and doping the active device region to form a link region which connects the first and second base regions.

Claim 17

The process of claim 13 wherein the step of forming a patterned masking layer comprises forming a patterned masking layer of Si 3 N 4 overlying the active device region and having an opening therein bounded by a wall.

Claim 18

The process of claim 13 wherein the step of forming metal silicide contacts comprises forming one of either cobalt silicide or titanium silicide contacts.