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JPS6425569A Expired / Lapsed JP ⏱️ 0.0 years remaining

Manufacture of semiconductor device

Assignee: Sony Corp
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Filing: 1987-07-22
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Granted: —
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Expires: 2007-07-22
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Abstract

Abstract PURPOSE:To decrease the resistance of a contact part at each electrode, by making poly Si for forming each electrode to remain on the insulating layer of a resistor, etching the insulating layer with the poly Si as a mask, and exposing the poly Si of a lead-out electrode and the poly Si of the resistor by self- alignment. CONSTITUTION:Poly Si is deposited on the entire surface by CVD, and a poly Si layer 25 is formed. Then ions of arsenic As are implanted at a high concentration. After SiO2 is deposited, annealing is performed, and the arsenic is diffused into a substrate 1. Thus an emitter region 26 is formed. Thereafter the SiO2 is etched away. Then, the poly Si layer 25 is patterned, and the poly Si layer 25 on an SiO2 layer 23 on a resistor forming region for a resistor 9 and the poly Si layer 25 on the SiO2 layer 23 on the element region of a lateral P-N-P transistor 3 are made to remain partially at the same time. Then, with the poly Si layers 25 as masks, anisotropic etching is performed. Thus the following parts are exposed: a base lead-out electrode 5 of a vertical N-P-N transistor 2; a poly Si layer 4 forming the resistor 9; and an emitter lead-out electrode 7 and a collector lead-out electrode 8 of the lateral P-N-P transistor 3.

Inventors

  • 👤 Hiroyuki Miwa
  • 👤 Minoru Nakamura
  • 👤 Akio Kashiwanuma

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-01 22:58
CPC Classifications
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