US5511024A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Dynamic random access memory system
Assignee: Rambus Inc
•
Filing: 1994-02-25
•
Granted: 1996-04-23
•
Expires: 2014-02-25
Abstract
Abstract As interfaces to DRAMs become more advanced and higher performance, the interfaces and signal lines required to support the interface become more expensive to implement. Therefore, it is desirable to minimize the number of signal lines and maximize the bandwidth of the signal lines interfacing to the DRAM in order to take advantage of the high performance of the signal lines in the interface. In the DRAM memory system of the present invention, the address and control lines and are combined and the information multiplexed such that the DRAM pins have roughly equal information rate at all times.
Inventors
- 👤 Frederick A. Ware
- 👤 John B. Dillon
- 👤 Richard M. Barth
- 👤 Billy W. Garrett, Jr.
- 👤 John G. Atwood, Jr.
- 👤 Michael P. Farmwald
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 14:54
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/06; G11C5/066
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
170 words
A dynamic random access memory (DRAM) system, comprising: a DRAM array accessed according to a row address and a column address; array address/control circuitry coupled to an external bus for receiving the row and column addresses and control information to access the DRAM array; data input/output circuitry coupled to the bus for receiving data to be written in the DRAM array during a write access of the DRAM array and for transmitting data read from the DRAM array to the bus during a read access of the DRAM array; latency control circuitry for controlling the latency incurred during the write access of the DRAM array to equal the latency incurred during the read access of the DRAM array; circuitry for interleaving the read and write accesses of the DRAM array, wherein when (1) the latency of the write access is controlled to be equal to that of the read access and (2) the read and write accesses are interleaved, each clock cycle of the bus is utilized to communicate information.
Claim 2
Dependent Claim
170 words
A dynamic random access memory (DRAM) system, comprising: a DRAM array accessed according to a row address and a column address; array address/control circuitry coupled to an external bus for receiving the row and column addresses and control information to access the DRAM array; data input/output circuitry coupled to the bus for receiving data to be written in the DRAM array during a write access of the DRAM array and for transmitting data read from the DRAM array to the bus during a read access of the DRAM array; latency control circuitry for controlling the latency incurred during the write access of the DRAM array to equal the latency incurred during the read access of the DRAM array; circuitry for interleaving the read and write accesses of the DRAM array, wherein when (1) the latency of the write access is controlled to be equal to that of the read access and (2) the read and write accesses are interleaved, each clock cycle of the bus is utilized to communicate information.
Claim 3
Dependent Claim
46 words
The DRAM system of claim 1, wherein the latency control circuitry further comprises a programmable counter the count of which is varied to allow the latency of the write access of the DRAM array to equal the latency of the read access of the DRAM array.
Claim 4
Dependent Claim
63 words
The DRAM system of claim 1, wherein the latency control circuitry further comprises (i) a latency register for storing latency information indicative of the latency of the write access, wherein the latency information stored in the latency register can be modified; (ii) control circuit for controlling the latency of the write access in accordance with the latency information stored in the latency register.
References Cited (Backward Citations)
US3821715A
Cited
US4333142A
Cited
JPS54128226A
Cited
WO1979000914A1
Cited
US4286321A
Cited
JPS5720979A
Cited
US4434474A
Cited
JPS5853082A
Cited
US4649516A
Cited
US4979145A
Cited
US5184320A
Cited
US5027329A
Cited
US5257237A
Cited
US4967398A
Cited
US5278974A
Cited
WO1991016680A1
Cited
US5243703A
Cited
US5115411A
Cited
US5119331A
Cited
US5142276A
Cited
US5265053A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-04-23 | 1999-10-23 | 2000-04-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-04-23 | 2003-10-23 | 2004-04-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-04-23 | 2007-10-23 | 2008-04-23 | $7700.00 | Window Closed / Lapsed |