US4434474A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Single pin time-sharing for serially inputting and outputting data from state machine register apparatus
Assignee: Boeing North American Inc
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Filing: 1981-05-15
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Granted: 1984-02-28
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Expires: 2001-05-15
Abstract
Abstract Synchronously clocked gating apparatus is illustrated for time multiplexing signals into and out of a register simultaneously whereby a single pin can be utilized for the two sets of data transfer rather than the two pins required in the prior art.
Inventors
- 👤 David W. Best
- 👤 Jeffrey D. Russell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:40
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/06; G11C5/066
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
165 words
Apparatus for inputting data to and outputting data from a register through single terminal means relative a reference potential comprising, in combination: single terminal means; first means for supplying a clock signal having first and second logic states; second means, connected to said first means and to said single terminal means for supplying input data bits to the single terminal means only when the clock signal is in the first logic state; unitary register means having a plurality of a data bit storage stage, including serial data input means connected to said single terminal means, and independent serial data output means and clock means; third means, connected between said serial data output means and said single terminal means and also connected to said first means, for supplying serial output data bits to said single terminal means when said clock signal is in the second logic state, the bits of the input and output data being supplied to said single terminal means in an interleaved fashion.
Claim 2
Dependent Claim
165 words
Apparatus for inputting data to and outputting data from a register through single terminal means relative a reference potential comprising, in combination: single terminal means; first means for supplying a clock signal having first and second logic states; second means, connected to said first means and to said single terminal means for supplying input data bits to the single terminal means only when the clock signal is in the first logic state; unitary register means having a plurality of a data bit storage stage, including serial data input means connected to said single terminal means, and independent serial data output means and clock means; third means, connected between said serial data output means and said single terminal means and also connected to said first means, for supplying serial output data bits to said single terminal means when said clock signal is in the second logic state, the bits of the input and output data being supplied to said single terminal means in an interleaved fashion.
Claim 3
Dependent Claim
50 words
Apparatus as claimed in claim 1 comprising, in addition: means connecting said first means to said register means for serially shifting the data bits within said register means between the input and output ports thereof, once for each pair of logic states of said clock signal of said first means.
Claim 4
Dependent Claim
37 words
Apparatus as claimed in claim 1 comprising, in addition: apparatus output means connected to said single terminal means for outputting data as received from said serial data output means of said register means via said third means.
Claim 5
Independent Claim
97 words
The method of communicating data across a single pin interface with respect to referenced potential comprising the steps of: outputting data bits from a multi-data bit register to the serial interface during a first time increment; inputting data bits to said register through said interface during a next adjacent time increment; and serially shifting data within said register one data bit position before repeating the above steps in a repetitious manner until all desired data is both output and input from and to the single said register respectively, the input and output data bits being time interleaved.
Claim 6
Independent Claim
97 words
The method of communicating data across a single pin interface with respect to referenced potential comprising the steps of: outputting data bits from a multi-data bit register to the serial interface during a first time increment; inputting data bits to said register through said interface during a next adjacent time increment; and serially shifting data within said register one data bit position before repeating the above steps in a repetitious manner until all desired data is both output and input from and to the single said register respectively, the input and output data bits being time interleaved.
Claim 7
Independent Claim
102 words
The method of simultaneously inputting and outputting data to and from a register through a single terminal interface with respect to ground comprising, the steps of: retrieving a first output data bit from an output of a serial multi-data bit register through the single terminal interface; supplying a first input data bit to an output of said serial register through the single terminal interface; shifting the data bits one bit position within the register; and repeating the above steps until the register is filled with new data, the input and output data bits appearing at said single terminal interface being time multiplexed.
Claim 8
Independent Claim
102 words
The method of simultaneously inputting and outputting data to and from a register through a single terminal interface with respect to ground comprising, the steps of: retrieving a first output data bit from an output of a serial multi-data bit register through the single terminal interface; supplying a first input data bit to an output of said serial register through the single terminal interface; shifting the data bits one bit position within the register; and repeating the above steps until the register is filled with new data, the input and output data bits appearing at said single terminal interface being time multiplexed.
Claim 9
Dependent Claim
100 words
Apparatus for simultaneously inputting and outputting data bits to and from a single register through a single terminal interface with respect to reference potential comprising, in combination: unitary multiple-data bit register means including data input means, data output means and shift signal input means; single terminal interface means; data output means connecting said data output of said output register means with said single terminal interface means; and data input means connecting said single terminal interface means to said input means of said register means, the input and output data appearing at said single terminal interface means being bit time multiplexed.
Claim 10
Dependent Claim
100 words
Apparatus for simultaneously inputting and outputting data bits to and from a single register through a single terminal interface with respect to reference potential comprising, in combination: unitary multiple-data bit register means including data input means, data output means and shift signal input means; single terminal interface means; data output means connecting said data output of said output register means with said single terminal interface means; and data input means connecting said single terminal interface means to said input means of said register means, the input and output data appearing at said single terminal interface means being bit time multiplexed.
Claim 11
Dependent Claim
110 words
Apparatus as claimed in claim 6 comprising, in addition: means for retrieving a first data output bit from said single terminal interface means as output by said output means of said serial register means; means for supplying a first input bit to said single terminal interface means for application to said input means of said unitary register means; and means for connection to said shift signal input means of said register means for shifting the data bits within said register means, the retrieval and supply of data bits along with the shifting of data bits after each retrieval and supply being repeated until the register is filled with new data.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1987-02-27 | 1987-08-29 | 1988-02-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1991-02-27 | 1991-08-29 | 1992-02-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1995-02-27 | 1995-08-29 | 1996-02-28 | $7700.00 | Window Closed / Lapsed |